a5c90e48b6
The SelectionDAG scheduling preference now becomes source order scheduling (machine scheduler generates better code -- even without there being a machine model defined for LoongArch yet). Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. This is similar to commit: 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec
126 lines
3.5 KiB
LLVM
126 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @or_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: or_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = or <16 x i8> %v0, %v1
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store <16 x i8> %v2, ptr %res
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ret void
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}
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define void @or_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: or_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = or <8 x i16> %v0, %v1
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store <8 x i16> %v2, ptr %res
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ret void
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}
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define void @or_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: or_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = or <4 x i32> %v0, %v1
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store <4 x i32> %v2, ptr %res
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ret void
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}
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define void @or_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: or_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = or <2 x i64> %v0, %v1
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store <2 x i64> %v2, ptr %res
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ret void
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}
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define void @or_u_v16i8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: or_u_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vori.b $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = or <16 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
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store <16 x i8> %v1, ptr %res
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ret void
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}
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define void @or_u_v8i16(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: or_u_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.h $vr1, 31
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = or <8 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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store <8 x i16> %v1, ptr %res
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ret void
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}
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define void @or_u_v4i32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: or_u_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.w $vr1, 31
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = or <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>
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store <4 x i32> %v1, ptr %res
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ret void
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}
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define void @or_u_v2i64(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: or_u_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.d $vr1, 31
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; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = or <2 x i64> %v0, <i64 31, i64 31>
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store <2 x i64> %v1, ptr %res
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ret void
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}
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