a5c90e48b6
The SelectionDAG scheduling preference now becomes source order scheduling (machine scheduler generates better code -- even without there being a machine model defined for LoongArch yet). Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. This is similar to commit: 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec
123 lines
3.5 KiB
LLVM
123 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @sub_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sub_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vsub.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = sub <16 x i8> %v0, %v1
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store <16 x i8> %v2, ptr %res
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ret void
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}
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define void @sub_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sub_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vsub.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = sub <8 x i16> %v0, %v1
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store <8 x i16> %v2, ptr %res
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ret void
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}
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define void @sub_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sub_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vsub.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = sub <4 x i32> %v0, %v1
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store <4 x i32> %v2, ptr %res
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ret void
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}
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define void @sub_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sub_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vsub.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = sub <2 x i64> %v0, %v1
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store <2 x i64> %v2, ptr %res
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ret void
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}
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define void @sub_v16i8_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sub_v16i8_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsubi.bu $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = sub <16 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
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store <16 x i8> %v1, ptr %res
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ret void
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}
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define void @sub_v8i16_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sub_v8i16_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsubi.hu $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = sub <8 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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store <8 x i16> %v1, ptr %res
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ret void
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}
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define void @sub_v4i32_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sub_v4i32_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsubi.wu $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = sub <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>
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store <4 x i32> %v1, ptr %res
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ret void
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}
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define void @sub_v2i64_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sub_v2i64_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsubi.du $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = sub <2 x i64> %v0, <i64 31, i64 31>
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store <2 x i64> %v1, ptr %res
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ret void
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}
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