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llvm-project
/
llvm
/
test
/
CodeGen
/
RISCV
/
GlobalISel
/
instruction-select
/
rvv
History
Michael Maitland
63c925ca80
[RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type
2024-04-03 15:56:08 -07:00
..
add.mir
…
anyext.mir
[RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type
2024-04-03 15:56:08 -07:00
icmp.mir
[RISCV][GISEL] Instruction selection for G_ICMP
2024-04-03 15:47:34 -07:00
select.mir
…
sext.mir
[RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type
2024-04-03 15:56:08 -07:00
sub.mir
…
vscale32.mir
[RISCV][GISEL] Legalize, regbankselect, and instruction-select G_VSCALE (
#85967
)
2024-03-26 20:17:22 -04:00
vscale64.mir
[RISCV][GISEL] Legalize, regbankselect, and instruction-select G_VSCALE (
#85967
)
2024-03-26 20:17:22 -04:00
zext.mir
[RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type
2024-04-03 15:56:08 -07:00
