c51ab483e6
Refer to RISCV, we will fix up the alignment if linker relaxation changes code size and breaks alignment. Insert enough Nops and emit R_LARCH_ALIGN relocation type so that linker could satisfy the alignment by removing Nops. It does so only in sections with the SHF_EXECINSTR flag. In LoongArch psABI v2.30, R_LARCH_ALIGN requires symbol index. The lowest 8 bits of addend represent alignment and the other bits of addend represent the maximum number of bytes to emit.
28 lines
968 B
ArmAsm
28 lines
968 B
ArmAsm
## A label difference separated by an alignment directive, when the
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## referenced symbols are in a non-executable section with instructions,
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## should generate ADD/SUB relocations.
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## https://github.com/llvm/llvm-project/pull/76552
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# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s \
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# RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK,RELAX %s
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# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s \
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# RUN: | llvm-readobj -r - | FileCheck %s
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.section ".dummy", "a"
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.L1:
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la.pcrel $t0, sym
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.p2align 3
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.L2:
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.dword .L2 - .L1
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# CHECK: Relocations [
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# CHECK-NEXT: Section ({{.*}}) .rela.dummy {
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# CHECK-NEXT: 0x0 R_LARCH_PCALA_HI20 sym 0x0
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# RELAX-NEXT: 0x0 R_LARCH_RELAX - 0x0
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# CHECK-NEXT: 0x4 R_LARCH_PCALA_LO12 sym 0x0
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# RELAX-NEXT: 0x4 R_LARCH_RELAX - 0x0
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# RELAX-NEXT: 0x8 R_LARCH_ADD64 .L2 0x0
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# RELAX-NEXT: 0x8 R_LARCH_SUB64 .L1 0x0
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# CHECK-NEXT: }
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# CHECK-NEXT: ]
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