4e0c1d98d3
Add new subset of Core Instructions (not full yet). Add appropriate operands description, modify asm parser, printer and code emitter. Modify tests to support new instructions. Differential Revision: https://reviews.llvm.org/D64834
67 lines
1.3 KiB
ArmAsm
67 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc %s -triple=xtensa -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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.align 4
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LBL0:
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# Instruction format RRR
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# CHECK-INST: extui a1, a2, 7, 8
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# CHECK: encoding: [0x20,0x17,0x74]
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extui a1, a2, 7, 8
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# Instruction format RRR
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# CHECK-INST: sll a10, a11
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# CHECK: encoding: [0x00,0xab,0xa1]
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sll a10, a11
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# Instruction format RRR
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# CHECK-INST: slli a5, a1, 15
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# CHECK: encoding: [0x10,0x51,0x11]
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slli a5, a1, 15
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# Instruction format RRR
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# CHECK-INST: sra a12, a3
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# CHECK: encoding: [0x30,0xc0,0xb1]
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sra a12, a3
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# Instruction format RRR
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# CHECK-INST: srai a8, a5, 0
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# CHECK: encoding: [0x50,0x80,0x21]
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srai a8, a5, 0
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# Instruction format RRR
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# CHECK-INST: src a3, a4, a5
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# CHECK: encoding: [0x50,0x34,0x81]
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src a3, a4, a5
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# Instruction format RRR
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# CHECK-INST: srl a6, a7
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# CHECK: encoding: [0x70,0x60,0x91]
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srl a6, a7
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# Instruction format RRR
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# CHECK-INST: srli a3, a4, 8
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# CHECK: encoding: [0x40,0x38,0x41]
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srli a3, a4, 8
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# Instruction format RRR
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# CHECK-INST: ssa8l a14
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# CHECK: encoding: [0x00,0x2e,0x40]
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ssa8l a14
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# Instruction format RRR
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# CHECK-INST: ssai 31
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# CHECK: encoding: [0x10,0x4f,0x40]
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ssai 31
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# Instruction format RRR
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# CHECK-INST: ssl a0
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# CHECK: encoding: [0x00,0x10,0x40]
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ssl a0
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# Instruction format RRR
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# CHECK-INST: ssr a2
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# CHECK: encoding: [0x00,0x02,0x40]
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ssr a2
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