37ef640785
When generating snippets for AArch64 with --opcode-index=-1, the code generator asserts on opcodes that are not supported according to CPU features. The same assertion can be triggered even when generating a serial snippet for a supported opcode if SERIAL_VIA_NON_MEMORY_INSTR execution mode is used and an unsupported instruction is chosen as the "other instruction". Unlike the first case, this one may result in flaky failures because the other instruction is randomly chosen from the instructions suitable for serializing execution. This patch adjusts TableGen emitter for *GenInstrInfo.inc to make possible to query for opcode availability instead of just asserting on unsupported ones. ~~ Huawei RRI, OS Lab Reviewed By: courbet Differential Revision: https://reviews.llvm.org/D146303
81 lines
2.4 KiB
C++
81 lines
2.4 KiB
C++
//===-- Target.cpp ----------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../Target.h"
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#define GET_AVAILABLE_OPCODE_CHECKER
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#include "AArch64GenInstrInfo.inc"
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namespace llvm {
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namespace exegesis {
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static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
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switch (RegBitWidth) {
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case 32:
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return AArch64::MOVi32imm;
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case 64:
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return AArch64::MOVi64imm;
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}
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llvm_unreachable("Invalid Value Width");
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}
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// Generates instruction to load an immediate value into a register.
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static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
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const APInt &Value) {
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if (Value.getBitWidth() > RegBitWidth)
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llvm_unreachable("Value must fit in the Register");
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return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
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.addReg(Reg)
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.addImm(Value.getZExtValue());
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}
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#include "AArch64GenExegesis.inc"
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namespace {
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class ExegesisAArch64Target : public ExegesisTarget {
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public:
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ExegesisAArch64Target()
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: ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
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private:
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std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
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const APInt &Value) const override {
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if (AArch64::GPR32RegClass.contains(Reg))
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return {loadImmediate(Reg, 32, Value)};
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if (AArch64::GPR64RegClass.contains(Reg))
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return {loadImmediate(Reg, 64, Value)};
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errs() << "setRegTo is not implemented, results will be unreliable\n";
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return {};
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}
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bool matchesArch(Triple::ArchType Arch) const override {
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return Arch == Triple::aarch64 || Arch == Triple::aarch64_be;
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}
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void addTargetSpecificPasses(PassManagerBase &PM) const override {
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// Function return is a pseudo-instruction that needs to be expanded
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PM.add(createAArch64ExpandPseudoPass());
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}
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};
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} // namespace
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static ExegesisTarget *getTheExegesisAArch64Target() {
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static ExegesisAArch64Target Target;
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return &Target;
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}
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void InitializeAArch64ExegesisTarget() {
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ExegesisTarget::registerTarget(getTheExegesisAArch64Target());
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}
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} // namespace exegesis
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} // namespace llvm
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