bed9efed71
MCSymbolizer::tryAddingSymbolicOperand() overloaded the Size parameter to specify either the instruction size or the operand size depending on the architecture. However, for proper symbolic disassembly on X86, we need to know both sizes, as an instruction can have two operands, and the instruction size cannot be reliably calculated based on the operand offset and its size. Hence, split Size into OpSize and InstSize. For X86, the new interface allows to fix a couple of issues: * Correctly adjust the value of PC-relative operands. * Set operand size to zero when the operand is specified implicitly. Differential Revision: https://reviews.llvm.org/D126101
422 lines
16 KiB
C++
422 lines
16 KiB
C++
//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file is part of the ARC Disassembler.
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///
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//===----------------------------------------------------------------------===//
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#include "ARC.h"
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#include "ARCRegisterInfo.h"
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#include "MCTargetDesc/ARCMCTargetDesc.h"
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#include "TargetInfo/ARCTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "arc-disassembler"
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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/// A disassembler class for ARC.
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class ARCDisassembler : public MCDisassembler {
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public:
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std::unique_ptr<MCInstrInfo const> const MCII;
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ARCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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Size = 4;
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// Read 2 16-bit values, but swap hi/lo parts.
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Insn =
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(Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
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return true;
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}
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static bool readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint64_t &Insn) {
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Size = 8;
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Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
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((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
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((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
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((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
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return true;
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}
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static bool readInstruction48(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint64_t &Insn) {
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Size = 6;
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Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
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((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
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((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
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return true;
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}
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static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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Size = 2;
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Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
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return true;
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}
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template <unsigned B>
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static DecodeStatus
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DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
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const MCDisassembler *Decoder = nullptr);
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template <unsigned B>
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static DecodeStatus
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DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
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const MCDisassembler *Decoder = nullptr);
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template <unsigned B>
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static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t,
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const MCDisassembler *);
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static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t,
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const MCDisassembler *);
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static const uint16_t GPR32DecoderTable[] = {
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ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
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ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
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ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
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ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
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ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
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static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32) {
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LLVM_DEBUG(dbgs() << "Not a GPR32 register.");
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return MCDisassembler::Fail;
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}
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unsigned Reg = GPR32DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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// Enumerates registers from ranges [r0-r3],[r12-r15].
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if (RegNo > 3)
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RegNo += 8; // 4 for r12, etc...
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
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}
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#include "ARCGenDisassemblerTables.inc"
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static unsigned decodeCField(unsigned Insn) {
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return fieldFromInstruction(Insn, 6, 6);
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}
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static unsigned decodeBField(unsigned Insn) {
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return (fieldFromInstruction(Insn, 12, 3) << 3) |
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fieldFromInstruction(Insn, 24, 3);
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}
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static unsigned decodeAField(unsigned Insn) {
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return fieldFromInstruction(Insn, 0, 6);
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}
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static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Dec) {
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// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
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unsigned S9 = Insn & 0x1ff;
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unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
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DecodeGPR32RegisterClass(Inst, R, Address, Dec);
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Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
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return MCDisassembler::Success;
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}
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static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address,
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uint64_t Value,
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const MCDisassembler *Decoder) {
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static const uint64_t AtLeast = 2;
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return (nullptr != Decoder && Decoder->tryAddingSymbolicOperand(
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Inst, Value, Address, true, 0, AtLeast, 0));
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}
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static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address,
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uint64_t Offset,
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const MCDisassembler *Decoder) {
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uint64_t NextAddress = Address + Offset;
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if (!DecodeSymbolicOperand(Inst, Address, NextAddress, Decoder))
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Inst.addOperand(MCOperand::createImm(Offset));
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}
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template <unsigned B>
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static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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static_assert(B > 0, "field is empty");
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DecodeSymbolicOperandOff(Inst, Address, SignExtend32<B>(InsnS), Decoder);
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return MCDisassembler::Success;
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}
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template <unsigned B>
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static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
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uint64_t /*Address*/,
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const MCDisassembler * /*Decoder*/) {
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static_assert(B > 0, "field is empty");
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Inst.addOperand(MCOperand::createImm(
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SignExtend32<B>(maskTrailingOnes<decltype(InsnS)>(B) & InsnS)));
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return MCDisassembler::Success;
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}
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template <unsigned B>
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static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
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uint64_t /*Address*/,
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const MCDisassembler * /*Decoder*/) {
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static_assert(B > 0, "field is empty");
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const unsigned max = (1u << B) - 1;
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Inst.addOperand(
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MCOperand::createImm(InsnS < max ? static_cast<int>(InsnS) : -1));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned SrcC, DstB, LImm;
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DstB = decodeBField(Insn);
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if (DstB != 62) {
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LLVM_DEBUG(dbgs() << "Decoding StLImm found non-limm register.");
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return MCDisassembler::Fail;
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}
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SrcC = decodeCField(Insn);
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DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder);
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LImm = (Insn >> 32);
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Inst.addOperand(MCOperand::createImm(LImm));
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Inst.addOperand(MCOperand::createImm(0));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned DstA, SrcB, LImm;
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LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n");
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SrcB = decodeBField(Insn);
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if (SrcB != 62) {
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LLVM_DEBUG(dbgs() << "Decoding LdLImm found non-limm register.");
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return MCDisassembler::Fail;
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}
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DstA = decodeAField(Insn);
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DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
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LImm = (Insn >> 32);
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Inst.addOperand(MCOperand::createImm(LImm));
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Inst.addOperand(MCOperand::createImm(0));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned DstA, SrcB;
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LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n");
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DstA = decodeAField(Insn);
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DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
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SrcB = decodeBField(Insn);
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DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder);
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if (decodeCField(Insn) != 62) {
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LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register.");
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return MCDisassembler::Fail;
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}
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Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32)));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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LLVM_DEBUG(dbgs() << "Decoding MOV_S h-register\n");
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using Field = decltype(Insn);
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Field H = fieldFromInstruction(Insn, 5, 3) |
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(fieldFromInstruction(Insn, 0, 2) << 3);
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Field G = fieldFromInstruction(Insn, 8, 3) |
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(fieldFromInstruction(Insn, 3, 2) << 3);
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auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
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Field Value) {
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if (30 == RegNum) {
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Inst.addOperand(MCOperand::createImm(Value));
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return MCDisassembler::Success;
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}
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return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
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};
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if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0))
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return MCDisassembler::Fail;
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return DecodeRegisterOrImm(H, Insn >> 16u);
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}
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static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned DstB;
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LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");
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DstB = decodeBField(Insn);
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DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
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using Field = decltype(Insn);
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Field U6Field = fieldFromInstruction(Insn, 6, 6);
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Inst.addOperand(MCOperand::createImm(U6Field));
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Field CCField = fieldFromInstruction(Insn, 0, 4);
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Inst.addOperand(MCOperand::createImm(CCField));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned DstB = decodeBField(Insn);
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DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
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using Field = decltype(Insn);
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Field U6 = fieldFromInstruction(Insn, 6, 6);
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Inst.addOperand(MCOperand::createImm(U6));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned DstB = decodeBField(Insn);
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DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
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using Field = decltype(Insn);
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Field Lower = fieldFromInstruction(Insn, 6, 6);
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Field Upper = fieldFromInstruction(Insn, 0, 5);
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Field Sign = fieldFromInstruction(Insn, 5, 1) ? -1 : 1;
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Field Result = Sign * ((Upper << 6) + Lower);
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Inst.addOperand(MCOperand::createImm(Result));
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return MCDisassembler::Success;
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}
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DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &cStream) const {
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MCDisassembler::DecodeStatus Result;
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if (Bytes.size() < 2) {
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Size = 0;
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return Fail;
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}
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uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
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// 0x00 -> 0x07 are 32-bit instructions.
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// 0x08 -> 0x1F are 16-bit instructions.
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if (DecodeByte < 0x08) {
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// 32-bit instruction.
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if (Bytes.size() < 4) {
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// Did we decode garbage?
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Size = 0;
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return Fail;
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}
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if (Bytes.size() >= 8) {
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// Attempt to decode 64-bit instruction.
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uint64_t Insn64;
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if (!readInstruction64(Bytes, Address, Size, Insn64))
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return Fail;
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Result =
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decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);
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if (Success == Result) {
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LLVM_DEBUG(dbgs() << "Successfully decoded 64-bit instruction.");
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return Result;
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}
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LLVM_DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit.");
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}
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uint32_t Insn32;
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if (!readInstruction32(Bytes, Address, Size, Insn32)) {
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return Fail;
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}
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// Calling the auto-generated decoder function.
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return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);
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} else {
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if (Bytes.size() >= 6) {
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// Attempt to treat as instr. with limm data.
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uint64_t Insn48;
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if (!readInstruction48(Bytes, Address, Size, Insn48))
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return Fail;
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Result =
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decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI);
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if (Success == Result) {
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LLVM_DEBUG(
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dbgs() << "Successfully decoded 16-bit instruction with limm.");
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return Result;
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}
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LLVM_DEBUG(
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dbgs() << "Not a 16-bit instruction with limm, try without it.");
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}
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uint32_t Insn16;
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if (!readInstruction16(Bytes, Address, Size, Insn16))
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return Fail;
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// Calling the auto-generated decoder function.
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return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);
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}
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}
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static MCDisassembler *createARCDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new ARCDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(getTheARCTarget(),
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createARCDisassembler);
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}
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