72901fe19e
Using the LSR or LSL aliases of UBFM can be faster on some CPUs, so it is worth changing 64 bit UBFM instructions, that are equivalent to 32 bit LSR/LSL operations, to 32 bit variants. This change folds the following patterns: * If `Imms == 31` and `Immr <= Imms`: `UBFMXri %0, Immr, Imms` -> `UBFMWri %0.sub_32, Immr, Imms` * If `Immr == Imms + 33`: `UBFMXri %0, Immr, Imms` -> `UBFMWri %0.sub_32, Immr - 32, Imms`
28 lines
889 B
LLVM
28 lines
889 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-apple-ios -fast-isel -verify-machineinstrs | FileCheck %s
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; Check that the kill flag is cleared between CSE'd instructions on their
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; imp-def'd registers.
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; The verifier would complain otherwise.
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define i64 @csed_impdef_killflag(i64 %a) {
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; CHECK-LABEL: csed_impdef_killflag:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: cmp x0, #0
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; CHECK-NEXT: mov x9, #2 ; =0x2
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; CHECK-NEXT: csel w8, wzr, w8, ne
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; CHECK-NEXT: mov x10, #3 ; =0x3
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; CHECK-NEXT: lsr w8, w8, #0
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; CHECK-NEXT: csel x9, x9, x10, ne
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; CHECK-NEXT: add x0, x9, x8
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; CHECK-NEXT: ret
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%1 = icmp ne i64 %a, 0
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%2 = select i1 %1, i32 0, i32 1
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%3 = icmp ne i64 %a, 0
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%4 = select i1 %3, i64 2, i64 3
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%5 = zext i32 %2 to i64
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%6 = add i64 %4, %5
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ret i64 %6
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}
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