c649fd34e9
This patch adds a new code transformation to the `MachineSink` pass, that tries to sink copies of an instruction, when the copies can be folded into the addressing modes of load/store instructions, or replace another instruction (currently, copies into a hard register). The criteria for performing the transformation is that: * the register pressure at the sink destination block must not exceed the register pressure limits * the latency and throughput of the load/store or the copy must not deteriorate * the original instruction must be deleted Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D152828
41 lines
1.2 KiB
LLVM
41 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand -aarch64-enable-sink-fold=true %s -o - | FileCheck %s
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define i32 @rndr(ptr %__addr) {
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; CHECK-LABEL: rndr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mrs x9, RNDR
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; CHECK-NEXT: mov x8, x0
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; CHECK-NEXT: cset w10, eq
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; CHECK-NEXT: str x9, [x8]
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; CHECK-NEXT: and w0, w10, #0x1
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; CHECK-NEXT: ret
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%1 = tail call { i64, i1 } @llvm.aarch64.rndr()
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%2 = extractvalue { i64, i1 } %1, 0
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%3 = extractvalue { i64, i1 } %1, 1
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store i64 %2, ptr %__addr, align 8
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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define i32 @rndrrs(ptr %__addr) {
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; CHECK-LABEL: rndrrs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mrs x9, RNDRRS
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; CHECK-NEXT: mov x8, x0
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; CHECK-NEXT: cset w10, eq
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; CHECK-NEXT: str x9, [x8]
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; CHECK-NEXT: and w0, w10, #0x1
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; CHECK-NEXT: ret
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%1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
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%2 = extractvalue { i64, i1 } %1, 0
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%3 = extractvalue { i64, i1 } %1, 1
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store i64 %2, ptr %__addr, align 8
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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declare { i64, i1 } @llvm.aarch64.rndr()
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declare { i64, i1 } @llvm.aarch64.rndrrs()
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