9fd75233ca
This is preparation work towards making such splats use Constant{Int,FP}
by default for scalable vectors.
105 lines
2.8 KiB
LLVM
105 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; SVE Logical Vector Immediate Unpredicated CodeGen
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;
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; ORR
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define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: orr_i8:
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; CHECK: orr z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%res = or <vscale x 16 x i8> %a, splat(i8 15)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: orr_i16:
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; CHECK: orr z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%res = or <vscale x 8 x i16> %a, splat(i16 64519)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: orr_i32:
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; CHECK: orr z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%res = or <vscale x 4 x i32> %a, splat(i32 16776960)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: orr_i64:
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; CHECK: orr z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%res = or <vscale x 2 x i64> %a, splat(i64 18445618173802708992)
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ret <vscale x 2 x i64> %res
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}
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; EOR
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define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: eor_i8:
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; CHECK: eor z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%res = xor <vscale x 16 x i8> %a, splat(i8 15)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: eor_i16:
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; CHECK: eor z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%res = xor <vscale x 8 x i16> %a, splat(i16 64519)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: eor_i32:
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; CHECK: eor z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%res = xor <vscale x 4 x i32> %a, splat(i32 16776960)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: eor_i64:
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; CHECK: eor z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%res = xor <vscale x 2 x i64> %a, splat(i64 18445618173802708992)
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ret <vscale x 2 x i64> %res
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}
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; AND
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define <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: and_i8:
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; CHECK: and z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%res = and <vscale x 16 x i8> %a, splat(i8 15)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: and_i16:
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; CHECK: and z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%res = and <vscale x 8 x i16> %a, splat(i16 64519)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: and_i32:
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; CHECK: and z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%res = and <vscale x 4 x i32> %a, splat(i32 16776960)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: and_i64:
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; CHECK: and z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%res = and <vscale x 2 x i64> %a, splat(i64 18445618173802708992)
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ret <vscale x 2 x i64> %res
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}
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