c2bd5c25b3
This patch implements a DAG combine whereby
```
a: v2i64 = ...
b: i64 = extract_vector_elt a, Constant:i64<n>
c: i32 = truncate b
```
Becomes
```
a: v2i64 = ...
b: v4i32 = AArch64ISD::NVCAST a
c: i32 = extract_vector_elt c, Constant:i64<2n>
```
The primary goal of this work is to enable the use of [INS
(element)](https://developer.arm.com/documentation/ddi0602/2024-09/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en)
when moving a truncated i32 element between vectors. This combine
canonicalises the structure of the DAG for all legal instances of the
pattern above (by removing the explicit `trunc` operator in this
specific case), allowing us to take advantage of existing ISEL patterns
for this behavior.
224 lines
6.4 KiB
LLVM
224 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; ANDV
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define i8 @andv_nxv8i8(<vscale x 8 x i8> %a) {
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; CHECK-LABEL: andv_nxv8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: andv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.and.nxv8i8(<vscale x 8 x i8> %a)
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ret i8 %res
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}
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define i32 @andv_nxv8i32(<vscale x 8 x i32> %a) {
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; CHECK-LABEL: andv_nxv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and z0.d, z0.d, z1.d
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: andv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.and.nxv8i32(<vscale x 8 x i32> %a)
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ret i32 %res
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}
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; ORV
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define i32 @orv_nxv2i32(<vscale x 2 x i32> %a) {
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; CHECK-LABEL: orv_nxv2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: orv d0, p0, z0.d
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %a)
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ret i32 %res
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}
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define i64 @orv_nxv8i64(<vscale x 8 x i64> %a) {
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; CHECK-LABEL: orv_nxv8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: orv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%res = call i64 @llvm.vector.reduce.or.nxv8i64(<vscale x 8 x i64> %a)
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ret i64 %res
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}
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; XORV
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define i16 @xorv_nxv2i16(<vscale x 2 x i16> %a) {
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; CHECK-LABEL: xorv_nxv2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: eorv d0, p0, z0.d
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %a)
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ret i16 %res
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}
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define i32 @xorv_nxv8i32(<vscale x 8 x i32> %a) {
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; CHECK-LABEL: xorv_nxv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: eorv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.xor.nxv8i32(<vscale x 8 x i32> %a)
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ret i32 %res
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}
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; UADDV
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define i16 @uaddv_nxv4i16(<vscale x 4 x i16> %a) {
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; CHECK-LABEL: uaddv_nxv4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: uaddv d0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %a)
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ret i16 %res
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}
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define i16 @uaddv_nxv16i16(<vscale x 16 x i16> %a) {
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; CHECK-LABEL: uaddv_nxv16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add z0.h, z0.h, z1.h
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: uaddv d0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.add.nxv16i16(<vscale x 16 x i16> %a)
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ret i16 %res
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}
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define i32 @uaddv_nxv16i32(<vscale x 16 x i32> %a) {
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; CHECK-LABEL: uaddv_nxv16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add z1.s, z1.s, z3.s
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; CHECK-NEXT: add z0.s, z0.s, z2.s
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: uaddv d0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %a)
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ret i32 %res
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}
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; UMINV
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define i32 @umin_nxv2i32(<vscale x 2 x i32> %a) {
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; CHECK-LABEL: umin_nxv2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and z0.d, z0.d, #0xffffffff
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: uminv d0, p0, z0.d
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %a)
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ret i32 %res
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}
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define i64 @umin_nxv4i64(<vscale x 4 x i64> %a) {
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; CHECK-LABEL: umin_nxv4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: uminv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%res = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %a)
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ret i64 %res
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}
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; SMINV
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define i8 @smin_nxv4i8(<vscale x 4 x i8> %a) {
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; CHECK-LABEL: smin_nxv4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: sxtb z0.s, p0/m, z0.s
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; CHECK-NEXT: sminv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %a)
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ret i8 %res
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}
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define i32 @smin_nxv8i32(<vscale x 8 x i32> %a) {
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; CHECK-LABEL: smin_nxv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: sminv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.smin.nxv8i32(<vscale x 8 x i32> %a)
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ret i32 %res
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}
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; UMAXV
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define i16 @smin_nxv16i16(<vscale x 16 x i16> %a) {
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; CHECK-LABEL: smin_nxv16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: umaxv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.umax.nxv16i16(<vscale x 16 x i16> %a)
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ret i16 %res
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}
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; SMAXV
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define i64 @smin_nxv8i64(<vscale x 8 x i64> %a) {
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; CHECK-LABEL: smin_nxv8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
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; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
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; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: smaxv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%res = call i64 @llvm.vector.reduce.smax.nxv8i64(<vscale x 8 x i64> %a)
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ret i64 %res
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}
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declare i8 @llvm.vector.reduce.and.nxv8i8(<vscale x 8 x i8>)
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declare i32 @llvm.vector.reduce.and.nxv8i32(<vscale x 8 x i32>)
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declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>)
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declare i64 @llvm.vector.reduce.or.nxv8i64(<vscale x 8 x i64>)
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declare i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16>)
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declare i32 @llvm.vector.reduce.xor.nxv8i32(<vscale x 8 x i32>)
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declare i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16>)
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declare i16 @llvm.vector.reduce.add.nxv16i16(<vscale x 16 x i16>)
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declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>)
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declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>)
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declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
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declare i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8>)
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declare i32 @llvm.vector.reduce.smin.nxv8i32(<vscale x 8 x i32>)
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declare i16 @llvm.vector.reduce.umax.nxv16i16(<vscale x 16 x i16>)
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declare i64 @llvm.vector.reduce.smax.nxv8i64(<vscale x 8 x i64>)
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