eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
73 lines
3.0 KiB
LLVM
73 lines
3.0 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S -stats 2>&1 | FileCheck %s
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;
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; A more complicated chain: 4 mul operations, so we expect 2 smlad calls.
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;
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; CHECK: %mac1{{\.}}054 = phi i32 [ [[V17:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
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; CHECK: [[V11:%[0-9]+]] = load i32, ptr %arrayidx, align 2
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; CHECK: [[V16:%[0-9]+]] = load i32, ptr %arrayidx4, align 2
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; CHECK: [[V9:%[0-9]+]] = load i32, ptr %arrayidx8, align 2
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; CHECK: [[ACC:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V9]], i32 [[V11]], i32 %mac1{{\.}}054)
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; CHECK: [[V14:%[0-9]+]] = load i32, ptr %arrayidx17, align 2
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; CHECK: [[V12:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V14]], i32 [[V16]], i32 [[ACC]])
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;
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; And we don't want to see a 3rd smlad:
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; CHECK-NOT: call i32 @llvm.arm.smlad
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;
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; CHECK: 2 arm-parallel-dsp - Number of smlad instructions generated
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;
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define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {
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entry:
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%cmp52 = icmp sgt i32 %arg, 0
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br i1 %cmp52, label %for.body.preheader, label %for.cond.cleanup
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add28, %for.body ]
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ret i32 %mac1.0.lcssa
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for.body.preheader:
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br label %for.body
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for.body:
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%mac1.054 = phi i32 [ %add28, %for.body ], [ 0, %for.body.preheader ]
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%i.053 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.053
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%0 = load i16, ptr %arrayidx, align 2
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%add1 = or disjoint i32 %i.053, 1
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%arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1
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%1 = load i16, ptr %arrayidx2, align 2
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%add3 = or disjoint i32 %i.053, 2
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%arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3
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%2 = load i16, ptr %arrayidx4, align 2
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%add5 = or disjoint i32 %i.053, 3
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%arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5
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%3 = load i16, ptr %arrayidx6, align 2
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%arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.053
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%4 = load i16, ptr %arrayidx8, align 2
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%conv = sext i16 %4 to i32
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%conv9 = sext i16 %0 to i32
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%mul = mul nsw i32 %conv, %conv9
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%arrayidx11 = getelementptr inbounds i16, ptr %arg2, i32 %add1
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%5 = load i16, ptr %arrayidx11, align 2
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%conv12 = sext i16 %5 to i32
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%conv13 = sext i16 %1 to i32
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%mul14 = mul nsw i32 %conv12, %conv13
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%arrayidx17 = getelementptr inbounds i16, ptr %arg2, i32 %add3
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%6 = load i16, ptr %arrayidx17, align 2
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%conv18 = sext i16 %6 to i32
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%conv19 = sext i16 %2 to i32
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%mul20 = mul nsw i32 %conv18, %conv19
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%arrayidx23 = getelementptr inbounds i16, ptr %arg2, i32 %add5
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%7 = load i16, ptr %arrayidx23, align 2
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%conv24 = sext i16 %7 to i32
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%conv25 = sext i16 %3 to i32
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%mul26 = mul nsw i32 %conv24, %conv25
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%add15 = add i32 %mul, %mac1.054
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%add21 = add i32 %add15, %mul14
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%add27 = add i32 %add21, %mul20
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%add28 = add i32 %add27, %mul26
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%add29 = add nuw nsw i32 %i.053, 4
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%cmp = icmp slt i32 %add29, %arg
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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}
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