5f058398ab
Similar to #83390, this marks AESD and AESE as commutative, as the logic of the instructions starts as a XOR between the two operands.
42 lines
1.3 KiB
LLVM
42 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc %s -o - -mtriple=armv8-none-eabi -mattr=+aes | FileCheck %s
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declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
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declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
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define arm_aapcs_vfpcc <16 x i8> @aese(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aese:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: aese.8 q0, q1
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; CHECK-NEXT: bx lr
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%r = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %r
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}
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define arm_aapcs_vfpcc <16 x i8> @aese_c(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aese_c:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: aese.8 q0, q1
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; CHECK-NEXT: bx lr
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%r = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %b, <16 x i8> %a)
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ret <16 x i8> %r
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}
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define arm_aapcs_vfpcc <16 x i8> @aesd(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aesd:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: aesd.8 q0, q1
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; CHECK-NEXT: bx lr
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%r = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %r
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}
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define arm_aapcs_vfpcc <16 x i8> @aesd_c(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aesd_c:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: aesd.8 q0, q1
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; CHECK-NEXT: bx lr
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%r = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %b, <16 x i8> %a)
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ret <16 x i8> %r
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}
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