llvm-project/llvm/test/CodeGen/ARM/bad-constraint.ll
eleviant 907b7d0f07
[ARM] Fix inline asm register validation for vector types (#152175)
Patch allows following piece of code to be successfully compiled:
```
register uint8x8_t V asm("d3") = vdup_n_u8(0xff);
```
2025-08-06 10:30:49 +02:00

32 lines
938 B
LLVM

; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s
; CHECK: error: couldn't allocate input reg for constraint '{d2}'
; CHECK-NEXT: error: couldn't allocate input reg for constraint '{s2}'
; CHECK-NEXT: error: couldn't allocate input reg for constraint '{d3}'
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8a-unknown-linux-gnueabihf"
@a = local_unnamed_addr global i32 0, align 4
define void @_Z1bv() local_unnamed_addr {
entry:
%0 = load i32, ptr @a, align 4
%conv = sext i32 %0 to i64
tail call void asm sideeffect "", "{d2}"(i64 %conv)
ret void
}
define void @_Z1cv() local_unnamed_addr {
entry:
%0 = load i32, ptr @a, align 4
%conv = sext i32 %0 to i64
tail call void asm sideeffect "", "{s2}"(i64 %conv)
ret void
}
define void @_Z1dv() local_unnamed_addr {
entry:
tail call void asm sideeffect "", "{d3}"(<16 x i8> splat (i8 -1))
ret void
}