b62826cc05
This is alternative to #145965 that allows RegisterSDNode to be handled without making a special case.
250 lines
14 KiB
LLVM
250 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=arm -mattr=+vfp4d16sp,-fullfp16 -stop-after=finalize-isel | FileCheck %s --check-prefixes=CHECK-CVT
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; RUN: llc < %s -mtriple=arm -mattr=+vfp4d16sp,+fullfp16 -stop-after=finalize-isel | FileCheck %s --check-prefixes=CHECK-FP16
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; Check that the output instructions have the same fast math flags as the input
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; fadd, even when f16 is legalized to f32.
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; FIXME: We don't get fast math flags on VCVTBSH because the outermost node in
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; the isel pattern is COPY_TO_REGCLASS and the fast math flags end up there.
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define half @normal_fadd(half %x, half %y) {
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; CHECK-CVT-LABEL: name: normal_fadd
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: normal_fadd
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add = fadd half %x, %y
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ret half %add
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}
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define half @fast_fadd(half %x, half %y) {
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; CHECK-CVT-LABEL: name: fast_fadd
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: fast_fadd
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf nsz arcp contract afn reassoc VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add = fadd fast half %x, %y
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ret half %add
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}
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define half @ninf_fadd(half %x, half %y) {
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; CHECK-CVT-LABEL: name: ninf_fadd
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: ninf_fadd
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add = fadd ninf half %x, %y
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ret half %add
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}
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; Check that when we have the right fast math flags the converts in between the
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; two fadds are removed.
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define half @normal_fadd_sequence(half %x, half %y, half %z) {
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; CHECK-CVT-LABEL: name: normal_fadd_sequence
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1, $r2
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]]
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
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; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]]
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; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: normal_fadd_sequence
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1, $r2
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add1 = fadd half %x, %y
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%add2 = fadd half %add1, %z
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ret half %add2
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}
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define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) {
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; CHECK-CVT-LABEL: name: nnan_ninf_contract_fadd_sequence
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1, $r2
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]]
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY6]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: nnan_ninf_contract_fadd_sequence
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1, $r2
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf contract VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nnan ninf contract VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add1 = fadd nnan ninf contract half %x, %y
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%add2 = fadd nnan ninf contract half %add1, %z
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ret half %add2
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}
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define half @ninf_fadd_sequence(half %x, half %y, half %z) {
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; CHECK-CVT-LABEL: name: ninf_fadd_sequence
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; CHECK-CVT: bb.0.entry:
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; CHECK-CVT-NEXT: liveins: $r0, $r1, $r2
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; CHECK-CVT-NEXT: {{ $}}
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; CHECK-CVT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2
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; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0
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; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]]
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; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]]
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; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]]
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; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
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; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]]
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; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg
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; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]]
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; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]]
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; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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;
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; CHECK-FP16-LABEL: name: ninf_fadd_sequence
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; CHECK-FP16: bb.0.entry:
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; CHECK-FP16-NEXT: liveins: $r0, $r1, $r2
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; CHECK-FP16-NEXT: {{ $}}
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; CHECK-FP16-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r2
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; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
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; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg
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; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg
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; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = ninf VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg
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; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]]
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; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
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entry:
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%add1 = fadd ninf half %x, %y
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%add2 = fadd ninf half %add1, %z
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ret half %add2
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}
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