llvm-project/llvm/test/CodeGen/ARM/inlineasm-vec-to-double.ll
eleviant 907b7d0f07
[ARM] Fix inline asm register validation for vector types (#152175)
Patch allows following piece of code to be successfully compiled:
```
register uint8x8_t V asm("d3") = vdup_n_u8(0xff);
```
2025-08-06 10:30:49 +02:00

15 lines
389 B
LLVM

; RUN: llc %s -filetype=asm -o - | FileCheck %s
; CHECK: vmov.i8 d3, #0xff
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv8a-unknown-linux-gnueabihf"
; Function Attrs: mustprogress noimplicitfloat nounwind
define void @cvt_vec() local_unnamed_addr {
entry:
tail call void asm sideeffect "", "{d3}"(<8 x i8> splat (i8 -1))
ret void
}