1e49670b31
This DAG combine replaces a floating-point load/store pair which has no other uses with an integer one, but did not copy the memory operand flags to the new instructions, resulting in it dropping the volatile flag. This optimisation is still valid if one or both of the instructions is volatile, so we can copy over the whole MachineMemOperand to generate volatile integer loads and stores where needed.
25 lines
1.3 KiB
LLVM
25 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=arm-none-eabi -stop-after=finalize-isel < %s | FileCheck %s
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define void @test(ptr %vol_one, ptr %p_in, ptr %p_out, i32 %n) {
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; CHECK-LABEL: name: test
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $r0, $r1, $r2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0
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; CHECK-NEXT: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[COPY1]], 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.p_in)
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; CHECK-NEXT: STRi12 killed [[LDRi12_]], [[COPY2]], 0, 14 /* CC::al */, $noreg :: (volatile store (s32) into %ir.vol_one)
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; CHECK-NEXT: [[LDRi12_1:%[0-9]+]]:gpr = LDRi12 [[COPY2]], 4, 14 /* CC::al */, $noreg :: (volatile load (s32) from %ir.vol_two)
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; CHECK-NEXT: STRi12 killed [[LDRi12_1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.p_out)
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; CHECK-NEXT: MOVPCLR 14 /* CC::al */, $noreg
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entry:
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%vol_two = getelementptr inbounds i8, ptr %vol_one, i32 4
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%a = load float, ptr %p_in, align 4
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store volatile float %a, ptr %vol_one, align 4
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%b = load volatile float, ptr %vol_two, align 4
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store float %b, ptr %p_out, align 4
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ret void
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}
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