d8d24c64fe
79845ed6dfc6511f99 folded some setcc(ashr) conditions to setcc, but got the condition for NE incorrect, using GT where it should be using GE.
404 lines
11 KiB
LLVM
404 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7a-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK7A
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; RUN: llc -mtriple=thumbv6m-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK6M
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; RUN: llc -mtriple=thumbv7m-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK7M
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK81M
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define i32 @xori64i32(i64 %a) {
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; CHECK7A-LABEL: xori64i32:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mvn r0, #-2147483648
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; CHECK7A-NEXT: eor r0, r0, r1, asr #31
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: xori64i32:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: asrs r1, r1, #31
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; CHECK6M-NEXT: ldr r0, .LCPI0_0
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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; CHECK6M-NEXT: .p2align 2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: .LCPI0_0:
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; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK7M-LABEL: xori64i32:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: mvn r0, #-2147483648
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; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: xori64i32:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: mvn r0, #-2147483648
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; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
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; CHECK81M-NEXT: bx lr
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%shr4 = ashr i64 %a, 63
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%conv5 = trunc i64 %shr4 to i32
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%xor = xor i32 %conv5, 2147483647
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ret i32 %xor
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}
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define i64 @selecti64i64(i64 %a) {
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; CHECK7A-LABEL: selecti64i64:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mvn r0, #-2147483648
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; CHECK7A-NEXT: eor r0, r0, r1, asr #31
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; CHECK7A-NEXT: asr r1, r1, #31
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: selecti64i64:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: asrs r1, r1, #31
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; CHECK6M-NEXT: ldr r0, .LCPI1_0
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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; CHECK6M-NEXT: .p2align 2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: .LCPI1_0:
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; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK7M-LABEL: selecti64i64:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: mvn r0, #-2147483648
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; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
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; CHECK7M-NEXT: asrs r1, r1, #31
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: selecti64i64:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: mvn r0, #-2147483648
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; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
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; CHECK81M-NEXT: asrs r1, r1, #31
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; CHECK81M-NEXT: bx lr
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%c = icmp sgt i64 %a, -1
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%s = select i1 %c, i64 2147483647, i64 -2147483648
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ret i64 %s
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}
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define i32 @selecti64i32(i64 %a) {
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; CHECK7A-LABEL: selecti64i32:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mvn r0, #-2147483648
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; CHECK7A-NEXT: eor r0, r0, r1, asr #31
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: selecti64i32:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: ldr r0, .LCPI2_0
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; CHECK6M-NEXT: cmp r1, #0
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; CHECK6M-NEXT: bge .LBB2_2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: adds r0, r0, #1
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; CHECK6M-NEXT: .LBB2_2:
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; CHECK6M-NEXT: bx lr
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; CHECK6M-NEXT: .p2align 2
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; CHECK6M-NEXT: @ %bb.3:
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; CHECK6M-NEXT: .LCPI2_0:
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; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK7M-LABEL: selecti64i32:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: mvn r0, #-2147483648
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; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: selecti64i32:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: mvn r0, #-2147483648
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; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
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; CHECK81M-NEXT: bx lr
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%c = icmp sgt i64 %a, -1
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%s = select i1 %c, i32 2147483647, i32 -2147483648
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ret i32 %s
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}
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define i64 @selecti32i64(i32 %a) {
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; CHECK7A-LABEL: selecti32i64:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mvn r1, #-2147483648
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; CHECK7A-NEXT: eor r2, r1, r0, asr #31
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; CHECK7A-NEXT: asr r1, r0, #31
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; CHECK7A-NEXT: mov r0, r2
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: selecti32i64:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: asrs r1, r0, #31
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; CHECK6M-NEXT: ldr r0, .LCPI3_0
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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; CHECK6M-NEXT: .p2align 2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: .LCPI3_0:
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; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK7M-LABEL: selecti32i64:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: mvn r1, #-2147483648
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; CHECK7M-NEXT: eor.w r2, r1, r0, asr #31
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; CHECK7M-NEXT: asrs r1, r0, #31
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; CHECK7M-NEXT: mov r0, r2
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: selecti32i64:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: mvn r1, #-2147483648
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; CHECK81M-NEXT: eor.w r2, r1, r0, asr #31
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; CHECK81M-NEXT: asrs r1, r0, #31
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; CHECK81M-NEXT: mov r0, r2
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; CHECK81M-NEXT: bx lr
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i64 2147483647, i64 -2147483648
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ret i64 %s
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}
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define i8 @xori32i8(i32 %a) {
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; CHECK7A-LABEL: xori32i8:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mov r1, #84
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; CHECK7A-NEXT: eor r0, r1, r0, asr #31
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: xori32i8:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: asrs r1, r0, #31
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; CHECK6M-NEXT: movs r0, #84
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: xori32i8:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: movs r1, #84
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; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: xori32i8:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: movs r1, #84
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; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
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; CHECK81M-NEXT: bx lr
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%shr4 = ashr i32 %a, 31
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%conv5 = trunc i32 %shr4 to i8
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%xor = xor i8 %conv5, 84
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ret i8 %xor
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}
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define i32 @selecti32i32(i32 %a) {
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; CHECK7A-LABEL: selecti32i32:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mov r1, #84
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; CHECK7A-NEXT: eor r0, r1, r0, asr #31
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: selecti32i32:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: asrs r1, r0, #31
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; CHECK6M-NEXT: movs r0, #84
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: selecti32i32:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: movs r1, #84
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; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: selecti32i32:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: movs r1, #84
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; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
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; CHECK81M-NEXT: bx lr
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i32 84, i32 -85
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ret i32 %s
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}
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define i8 @selecti32i8(i32 %a) {
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; CHECK7A-LABEL: selecti32i8:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: mov r1, #84
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; CHECK7A-NEXT: eor r0, r1, r0, asr #31
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: selecti32i8:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: asrs r1, r0, #31
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; CHECK6M-NEXT: movs r0, #84
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: selecti32i8:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: movs r1, #84
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; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: selecti32i8:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: movs r1, #84
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; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
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; CHECK81M-NEXT: bx lr
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i8 84, i8 -85
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ret i8 %s
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}
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define i32 @selecti8i32(i8 %a) {
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; CHECK7A-LABEL: selecti8i32:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: sxtb r0, r0
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; CHECK7A-NEXT: mov r1, #84
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; CHECK7A-NEXT: eor r0, r1, r0, asr #7
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: selecti8i32:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: sxtb r0, r0
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; CHECK6M-NEXT: asrs r1, r0, #7
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; CHECK6M-NEXT: movs r0, #84
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; CHECK6M-NEXT: eors r0, r1
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: selecti8i32:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: sxtb r0, r0
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; CHECK7M-NEXT: movs r1, #84
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; CHECK7M-NEXT: eor.w r0, r1, r0, asr #7
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: selecti8i32:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: sxtb r0, r0
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; CHECK81M-NEXT: movs r1, #84
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; CHECK81M-NEXT: eor.w r0, r1, r0, asr #7
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; CHECK81M-NEXT: bx lr
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%c = icmp sgt i8 %a, -1
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%s = select i1 %c, i32 84, i32 -85
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ret i32 %s
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}
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define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
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; CHECK7A-LABEL: icmpasreq:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: cmp r0, #0
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; CHECK7A-NEXT: movpl r1, r2
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; CHECK7A-NEXT: mov r0, r1
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: icmpasreq:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: cmp r0, #0
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; CHECK6M-NEXT: bmi .LBB8_2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: mov r1, r2
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; CHECK6M-NEXT: .LBB8_2:
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; CHECK6M-NEXT: mov r0, r1
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: icmpasreq:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: cmp r0, #0
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; CHECK7M-NEXT: it pl
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; CHECK7M-NEXT: movpl r1, r2
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; CHECK7M-NEXT: mov r0, r1
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: icmpasreq:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: cmp r0, #0
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; CHECK81M-NEXT: csel r0, r1, r2, mi
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; CHECK81M-NEXT: bx lr
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%sh = ashr i32 %input, 31
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%c = icmp eq i32 %sh, -1
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%s = select i1 %c, i32 %a, i32 %b
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ret i32 %s
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}
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define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
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; CHECK7A-LABEL: icmpasrne:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: cmn r0, #1
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; CHECK7A-NEXT: movle r1, r2
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; CHECK7A-NEXT: mov r0, r1
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: icmpasrne:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: cmp r0, #0
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; CHECK6M-NEXT: bge .LBB9_2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: mov r1, r2
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; CHECK6M-NEXT: .LBB9_2:
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; CHECK6M-NEXT: mov r0, r1
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: icmpasrne:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: cmp.w r0, #-1
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; CHECK7M-NEXT: it le
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; CHECK7M-NEXT: movle r1, r2
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; CHECK7M-NEXT: mov r0, r1
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: icmpasrne:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: cmp.w r0, #-1
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; CHECK81M-NEXT: csel r0, r1, r2, gt
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; CHECK81M-NEXT: bx lr
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%sh = ashr i32 %input, 31
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%c = icmp ne i32 %sh, -1
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%s = select i1 %c, i32 %a, i32 %b
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ret i32 %s
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}
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define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
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; CHECK7A-LABEL: oneusecmp:
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; CHECK7A: @ %bb.0:
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; CHECK7A-NEXT: cmp r0, #0
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; CHECK7A-NEXT: movmi r1, r2
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; CHECK7A-NEXT: mov r2, #127
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; CHECK7A-NEXT: eor r0, r2, r0, asr #31
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; CHECK7A-NEXT: add r0, r0, r1
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; CHECK7A-NEXT: bx lr
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;
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; CHECK6M-LABEL: oneusecmp:
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; CHECK6M: @ %bb.0:
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; CHECK6M-NEXT: cmp r0, #0
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; CHECK6M-NEXT: bmi .LBB10_2
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; CHECK6M-NEXT: @ %bb.1:
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; CHECK6M-NEXT: mov r2, r1
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; CHECK6M-NEXT: .LBB10_2:
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; CHECK6M-NEXT: asrs r0, r0, #31
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; CHECK6M-NEXT: movs r1, #127
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; CHECK6M-NEXT: eors r1, r0
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; CHECK6M-NEXT: adds r0, r1, r2
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; CHECK6M-NEXT: bx lr
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;
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; CHECK7M-LABEL: oneusecmp:
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; CHECK7M: @ %bb.0:
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; CHECK7M-NEXT: cmp r0, #0
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; CHECK7M-NEXT: it mi
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; CHECK7M-NEXT: movmi r1, r2
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; CHECK7M-NEXT: movs r2, #127
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; CHECK7M-NEXT: eor.w r0, r2, r0, asr #31
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; CHECK7M-NEXT: add r0, r1
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; CHECK7M-NEXT: bx lr
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;
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; CHECK81M-LABEL: oneusecmp:
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; CHECK81M: @ %bb.0:
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; CHECK81M-NEXT: cmp r0, #0
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; CHECK81M-NEXT: csel r1, r2, r1, mi
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; CHECK81M-NEXT: movs r2, #127
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; CHECK81M-NEXT: eor.w r0, r2, r0, asr #31
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; CHECK81M-NEXT: add r0, r1
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; CHECK81M-NEXT: bx lr
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%c = icmp sle i32 %a, -1
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%s = select i1 %c, i32 -128, i32 127
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%s2 = select i1 %c, i32 %d, i32 %b
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%x = add i32 %s, %s2
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ret i32 %x
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}
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