d19218e507
When we have a floating-point operation that a target doesn't support for a given type, but does support for a wider type, then there are two ways this can be handled: * If the target doesn't have any registers at all of this type then LegalizeTypes will convert the operation. * If we do have registers but no operation for this type, then the operation action will be Promote and it's handled in PromoteNode. In both cases the operation at the wider type, and the conversion operations to and from that type, should have the same fast math flags as the original operation. This is being done in preparation for a DAGCombine patch which makes use of these fast math flags.
187 lines
5.9 KiB
LLVM
187 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
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declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
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declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
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declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
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declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128>)
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define half @test_v4f16(<4 x half> %a) nounwind {
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; CHECK-LABEL: test_v4f16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: mov r4, #255
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; CHECK-NEXT: mov r8, r3
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; CHECK-NEXT: orr r4, r4, #65280
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; CHECK-NEXT: mov r5, r2
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; CHECK-NEXT: and r0, r0, r4
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; CHECK-NEXT: mov r6, r1
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r7, r0
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; CHECK-NEXT: and r0, r6, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r6, r0
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; CHECK-NEXT: mov r0, r7
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; CHECK-NEXT: mov r1, r6
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; CHECK-NEXT: bl __aeabi_fcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movne r6, r7
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; CHECK-NEXT: mov r0, r6
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; CHECK-NEXT: bl __aeabi_f2h
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; CHECK-NEXT: mov r6, r0
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; CHECK-NEXT: and r0, r5, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: and r0, r6, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: mov r6, r0
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; CHECK-NEXT: bl __aeabi_fcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movne r5, r6
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: bl __aeabi_f2h
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; CHECK-NEXT: and r0, r0, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: and r0, r8, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r4, r0
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: bl __aeabi_fcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movne r4, r5
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl __aeabi_f2h
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; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
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ret half %b
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}
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define float @test_v4f32(<4 x float> %a) nounwind {
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; CHECK-LABEL: test_v4f32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: mov r6, r2
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; CHECK-NEXT: mov r5, r1
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; CHECK-NEXT: mov r7, r0
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; CHECK-NEXT: bl __aeabi_fcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: mov r1, r6
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; CHECK-NEXT: movne r5, r7
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: bl __aeabi_fcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: moveq r5, r6
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: bl __aeabi_fcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: moveq r5, r4
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: pop {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
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ret float %b
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}
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define double @test_v2f64(<2 x double> %a) nounwind {
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; CHECK-LABEL: test_v2f64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: mov r6, r2
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; CHECK-NEXT: mov r8, r1
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; CHECK-NEXT: mov r7, r0
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; CHECK-NEXT: bl __aeabi_dcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: mov r5, r6
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; CHECK-NEXT: mov r0, r7
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; CHECK-NEXT: mov r1, r8
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; CHECK-NEXT: mov r2, r6
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; CHECK-NEXT: mov r3, r4
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; CHECK-NEXT: movne r5, r7
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; CHECK-NEXT: bl __aeabi_dcmplt
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: mov r0, r5
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; CHECK-NEXT: movne r4, r8
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
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ret double %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK-NEXT: .pad #28
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; CHECK-NEXT: sub sp, sp, #28
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; CHECK-NEXT: ldr r5, [sp, #76]
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; CHECK-NEXT: mov r8, r3
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; CHECK-NEXT: ldr r6, [sp, #72]
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; CHECK-NEXT: mov r9, r2
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; CHECK-NEXT: ldr r4, [sp, #68]
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; CHECK-NEXT: mov r10, r1
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; CHECK-NEXT: ldr r7, [sp, #64]
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; CHECK-NEXT: mov r11, r0
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; CHECK-NEXT: str r5, [sp, #12]
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; CHECK-NEXT: str r6, [sp, #8]
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; CHECK-NEXT: str r4, [sp, #4]
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; CHECK-NEXT: str r7, [sp]
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; CHECK-NEXT: bl __lttf2
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; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
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; CHECK-NEXT: mov r0, r11
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; CHECK-NEXT: mov r1, r10
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; CHECK-NEXT: mov r2, r9
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; CHECK-NEXT: mov r3, r8
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; CHECK-NEXT: str r7, [sp]
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; CHECK-NEXT: stmib sp, {r4, r6}
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; CHECK-NEXT: str r5, [sp, #12]
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; CHECK-NEXT: bl __lttf2
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; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
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; CHECK-NEXT: mov r0, r11
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; CHECK-NEXT: mov r1, r10
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; CHECK-NEXT: mov r2, r9
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; CHECK-NEXT: mov r3, r8
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; CHECK-NEXT: str r7, [sp]
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; CHECK-NEXT: stmib sp, {r4, r6}
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; CHECK-NEXT: str r5, [sp, #12]
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; CHECK-NEXT: bl __lttf2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
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; CHECK-NEXT: str r7, [sp]
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; CHECK-NEXT: movmi r7, r11
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
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; CHECK-NEXT: stmib sp, {r4, r6}
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; CHECK-NEXT: movmi r4, r10
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: mov r0, r11
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; CHECK-NEXT: mov r1, r10
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; CHECK-NEXT: mov r2, r9
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; CHECK-NEXT: mov r3, r8
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; CHECK-NEXT: str r5, [sp, #12]
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; CHECK-NEXT: movmi r6, r9
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; CHECK-NEXT: bl __lttf2
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: mov r0, r7
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; CHECK-NEXT: movmi r5, r8
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: mov r2, r6
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; CHECK-NEXT: mov r3, r5
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; CHECK-NEXT: add sp, sp, #28
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; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
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ret fp128 %b
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}
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