ebbc5de7db
The m68k backend will always emit external calls (including libcalls) with PC-relative PLT relocations, even when in non-pic mode or -fno-plt is used. This is unexpected, as other function calls are emitted with absolute addressing, and a static code modes suggests that there is no PLT. It also leads to a miscompilation where the call instruction emitted expects an immediate address, while the relocation emitted for that instruction is PC-relative. This miscompilation can even be seen in the default C function in godbolt: https://godbolt.org/z/zEoazovzo Fix the issue by classifying external function references based upon the pic mode. This triggers a change in the static code model, making it more in line with the expected behaviour and allowing use of this backend in more bare-metal situations where a PLT does not exist. The change avoids the issue where we emit a PLT32 relocation for an absolute call, and makes libcalls and other external calls use absolute addressing modes when a static code model is desired. Further work should be done in instruction lowering and validation to ensure that miscompilations of the same type don't occur.
49 lines
1.3 KiB
LLVM
49 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=m68k < %s | FileCheck %s
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; (Copied from test/CodeGen/X86/gcc_except_table.ll)
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; Testing whether exception pointer register (d0) and exception selector
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; register (d1) are correctly used by landing and EH pad, respectively.
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@_ZTIi = external constant ptr
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define i32 @foo() uwtable ssp personality ptr @__gxx_personality_v0 {
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; CHECK-LABEL: foo:
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; CHECK: .Lfunc_begin0:
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; CHECK-NEXT: .cfi_startproc
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; CHECK-NEXT: .cfi_personality 0, __gxx_personality_v0
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; CHECK-NEXT: .cfi_lsda 0, .Lexception0
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; CHECK-NEXT: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: .cfi_def_cfa_offset -8
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; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: jsr _Z1fv
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; CHECK-NEXT: .Ltmp1:
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; CHECK-NEXT: ; %bb.1: ; %try.cont
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; CHECK-NEXT: moveq #0, %d0
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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; CHECK-NEXT: .LBB0_2: ; %lpad
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; CHECK-NEXT: .Ltmp2:
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; CHECK-NEXT: move.l %d0, (%sp)
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; CHECK-NEXT: jsr _Unwind_Resume
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entry:
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invoke void @_Z1fv() optsize
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to label %try.cont unwind label %lpad
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lpad:
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%0 = landingpad { ptr, i32 }
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cleanup
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catch ptr @_ZTIi
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br label %eh.resume
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try.cont:
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ret i32 0
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eh.resume:
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resume { ptr, i32 } %0
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}
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declare void @_Z1fv() optsize
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declare i32 @__gxx_personality_v0(...)
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