c2e7c9cb33
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`. This is because IRTranslator uses SExt for indices. In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt. This change includes both documentation, SelectionDAG and IRTranslator. We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86 This patch fixes issue #57452. Differential Revision: https://reviews.llvm.org/D132978
181 lines
5.1 KiB
LLVM
181 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
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define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
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; CHECK-64-LABEL: test1:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: clrldi 3, 3, 32
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; CHECK-64-NEXT: vextublx 3, 3, 2
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; CHECK-64-NEXT: clrldi 3, 3, 56
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test1:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: addi 4, 1, -16
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; CHECK-32-NEXT: clrlwi 3, 3, 28
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lbzx 3, 4, 3
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 %index
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ret i8 %vecext
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}
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define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
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; CHECK-64-LABEL: test2:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: clrldi 3, 3, 32
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; CHECK-64-NEXT: vextublx 3, 3, 2
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; CHECK-64-NEXT: extsb 3, 3
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test2:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: addi 4, 1, -16
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; CHECK-32-NEXT: clrlwi 3, 3, 28
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lbzx 3, 4, 3
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; CHECK-32-NEXT: extsb 3, 3
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 %index
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ret i8 %vecext
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}
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define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
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; CHECK-64-LABEL: test3:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: clrldi 3, 3, 32
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; CHECK-64-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-64-NEXT: vextuhlx 3, 3, 2
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; CHECK-64-NEXT: clrldi 3, 3, 48
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test3:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: addi 4, 1, -16
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; CHECK-32-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lhzx 3, 4, 3
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 %index
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ret i16 %vecext
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}
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define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
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; CHECK-64-LABEL: test4:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: clrldi 3, 3, 32
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; CHECK-64-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-64-NEXT: vextuhlx 3, 3, 2
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; CHECK-64-NEXT: extsh 3, 3
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test4:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: addi 4, 1, -16
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; CHECK-32-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lhax 3, 4, 3
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 %index
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ret i16 %vecext
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}
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define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
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; CHECK-64-LABEL: test5:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: clrldi 3, 3, 32
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; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-64-NEXT: vextuwlx 3, 3, 2
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test5:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: addi 4, 1, -16
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; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lwzx 3, 4, 3
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %index
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ret i32 %vecext
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}
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define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
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; CHECK-64-LABEL: test6:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: clrldi 3, 3, 32
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; CHECK-64-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-64-NEXT: vextuwlx 3, 3, 2
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; CHECK-64-NEXT: extsw 3, 3
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test6:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: addi 4, 1, -16
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; CHECK-32-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lwzx 3, 4, 3
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %index
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ret i32 %vecext
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}
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; Test with immediate index
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define zeroext i8 @test7(<16 x i8> %a) {
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; CHECK-64-LABEL: test7:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: li 3, 1
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; CHECK-64-NEXT: vextublx 3, 3, 2
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; CHECK-64-NEXT: clrldi 3, 3, 56
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test7:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lbz 3, -15(1)
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 1
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ret i8 %vecext
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}
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define zeroext i16 @test8(<8 x i16> %a) {
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; CHECK-64-LABEL: test8:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: li 3, 2
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; CHECK-64-NEXT: vextuhlx 3, 3, 2
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; CHECK-64-NEXT: clrldi 3, 3, 48
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test8:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lhz 3, -14(1)
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; CHECK-32-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 1
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ret i16 %vecext
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}
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define zeroext i32 @test9(<4 x i32> %a) {
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; CHECK-64-LABEL: test9:
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; CHECK-64: # %bb.0:
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; CHECK-64-NEXT: li 3, 12
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; CHECK-64-NEXT: vextuwlx 3, 3, 2
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test9:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: stxv 34, -16(1)
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; CHECK-32-NEXT: lwz 3, -4(1)
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; CHECK-32-NEXT: blr
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%vecext = extractelement <4 x i32> %a, i32 3
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ret i32 %vecext
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}
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