a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
75 lines
2.5 KiB
LLVM
75 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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define dso_local void @calc_buffer() local_unnamed_addr #0 {
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; CHECK-LABEL: calc_buffer:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld r3, 0(r3)
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; CHECK-NEXT: sradi r4, r3, 53
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; CHECK-NEXT: addi r4, r4, 1
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; CHECK-NEXT: cmpldi r4, 1
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; CHECK-NEXT: bgt cr0, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mr r4, r3
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: clrldi r4, r3, 53
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; CHECK-NEXT: addi r4, r4, 2047
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; CHECK-NEXT: or r4, r4, r3
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; CHECK-NEXT: rldicr r4, r4, 0, 52
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: rldicl r6, r3, 10, 54
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; CHECK-NEXT: std r4, -32(r1)
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; CHECK-NEXT: rldicl r5, r3, 63, 1
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; CHECK-NEXT: clrldi r4, r3, 63
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; CHECK-NEXT: addi r6, r6, 1
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; CHECK-NEXT: cmpldi r6, 1
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; CHECK-NEXT: or r4, r4, r5
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; CHECK-NEXT: ble cr0, .LBB0_5
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; CHECK-NEXT: # %bb.4:
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; CHECK-NEXT: clrldi r4, r4, 53
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; CHECK-NEXT: addi r4, r4, 2047
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; CHECK-NEXT: or r4, r4, r5
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; CHECK-NEXT: rldicl r4, r4, 53, 11
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; CHECK-NEXT: rldicl r4, r4, 11, 1
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: cmpdi r3, 0
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; CHECK-NEXT: std r4, -24(r1)
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; CHECK-NEXT: bc 12, lt, .LBB0_7
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; CHECK-NEXT: # %bb.6:
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; CHECK-NEXT: lfd f0, -32(r1)
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; CHECK-NEXT: fcfid f0, f0
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; CHECK-NEXT: frsp f0, f0
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; CHECK-NEXT: b .LBB0_8
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; CHECK-NEXT: .LBB0_7:
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; CHECK-NEXT: lfd f0, -24(r1)
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; CHECK-NEXT: fcfid f0, f0
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; CHECK-NEXT: frsp f0, f0
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; CHECK-NEXT: fadds f0, f0, f0
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; CHECK-NEXT: .LBB0_8:
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; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-NEXT: lfs f1, .LCPI0_0@toc@l(r3)
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; CHECK-NEXT: fsubs f2, f0, f1
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; CHECK-NEXT: fctidz f2, f2
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; CHECK-NEXT: stfd f2, -8(r1)
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; CHECK-NEXT: fctidz f2, f0
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; CHECK-NEXT: fcmpu cr0, f0, f1
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; CHECK-NEXT: stfd f2, -16(r1)
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; CHECK-NEXT: blt cr0, .LBB0_10
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; CHECK-NEXT: # %bb.9:
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; CHECK-NEXT: ld r3, -8(r1)
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; CHECK-NEXT: li r4, 1
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; CHECK-NEXT: rldic r4, r4, 63, 0
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: std r3, 0(r3)
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; CHECK-NEXT: .LBB0_10:
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; CHECK-NEXT: ld r3, -16(r1)
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; CHECK-NEXT: std r3, 0(r3)
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%load_initial = load i64, ptr poison, align 8
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%conv39 = uitofp i64 %load_initial to float
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%add48 = fadd float 0.000000e+00, %conv39
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%conv49 = fptoui float %add48 to i64
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store i64 %conv49, ptr poison, align 8
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unreachable
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}
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