8e901c255d
We can decide whether to expand isel or not in instruction selection pass and early-if-conversion pass. The transformation implemented in PPCExpandISel can be retired considering PPC backend doesn't generate `isel` instructions post-RA. Also if we are seeking performant branch-or-isel decision, we can turn to selectoptimize pass. --------- Co-authored-by: Kai Luo <lkail@cn.ibm.com>
69 lines
2.8 KiB
LLVM
69 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; Verify that we get the code sequence needed to avoid double-rounding.
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; Note that only parts of the sequence are checked for here, to allow
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; for minor code generation differences.
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -mattr=-isel < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL
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; Also check that with -enable-unsafe-fp-math we do not get that extra
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; code sequence. Simply verify that there is no "isel" present.
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
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; CHECK-UNSAFE-NOT: isel
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @test(i64 %x) nounwind readnone {
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; Verify that we get the code sequence needed to avoid double-rounding.
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; Note that only parts of the sequence are checked for here, to allow
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; for minor code generation differences.
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; Also check that with -enable-unsafe-fp-math we do not get that extra
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; code sequence. Simply verify that there is no "isel" present.
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: clrldi 4, 3, 53
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; CHECK-NEXT: sradi 5, 3, 53
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; CHECK-NEXT: addi 4, 4, 2047
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; CHECK-NEXT: addi 5, 5, 1
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; CHECK-NEXT: or 4, 4, 3
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; CHECK-NEXT: cmpldi 5, 1
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; CHECK-NEXT: rldicr 4, 4, 0, 52
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: std 3, -8(1)
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; CHECK-NEXT: lfd 0, -8(1)
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; CHECK-NEXT: xscvsxddp 0, 0
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; CHECK-NEXT: frsp 1, 0
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; CHECK-NEXT: blr
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;
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; CHECK-NO-ISEL-LABEL: test:
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; CHECK-NO-ISEL: # %bb.0: # %entry
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; CHECK-NO-ISEL-NEXT: sradi 4, 3, 53
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; CHECK-NO-ISEL-NEXT: addi 4, 4, 1
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; CHECK-NO-ISEL-NEXT: cmpldi 4, 1
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; CHECK-NO-ISEL-NEXT: bc 4, 1, .LBB0_2
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; CHECK-NO-ISEL-NEXT: # %bb.1:
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; CHECK-NO-ISEL-NEXT: clrldi 4, 3, 53
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; CHECK-NO-ISEL-NEXT: addi 4, 4, 2047
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; CHECK-NO-ISEL-NEXT: or 3, 4, 3
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; CHECK-NO-ISEL-NEXT: rldicr 3, 3, 0, 52
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; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry
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; CHECK-NO-ISEL-NEXT: std 3, -8(1)
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; CHECK-NO-ISEL-NEXT: lfd 0, -8(1)
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; CHECK-NO-ISEL-NEXT: xscvsxddp 0, 0
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; CHECK-NO-ISEL-NEXT: frsp 1, 0
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; CHECK-NO-ISEL-NEXT: blr
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;
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; CHECK-UNSAFE-LABEL: test:
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; CHECK-UNSAFE: # %bb.0: # %entry
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; CHECK-UNSAFE-NEXT: std 3, -8(1)
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; CHECK-UNSAFE-NEXT: lfd 0, -8(1)
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; CHECK-UNSAFE-NEXT: xscvsxddp 0, 0
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; CHECK-UNSAFE-NEXT: frsp 1, 0
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; CHECK-UNSAFE-NEXT: blr
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entry:
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%conv = sitofp i64 %x to float
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ret float %conv
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}
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