a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
192 lines
7.0 KiB
LLVM
192 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck -check-prefixes=CHECKLX %s
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECKAIX %s
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECKAIX32 %s
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; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
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; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
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; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler
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; to insert a save TOC to stack before the call and load into X2 to restore TOC
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; after. By communicating to Machine LICM that X2 is guaranteed to have the
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; same value before and after BCTRL_LDinto_toc, these instructions can be
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; hoisted out of bb.3.if.end to outside of the loop.
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; Pre Machine LICM MIR
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;
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;body:
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; bb.0.entry:
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; successors: %bb.2.if.then(0x40000000), %bb.3.if.end(0x40000000)
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; liveins: %x3
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;
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; %4 = COPY %x3
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; %5 = ADDIStocHA8 %x2, @ga
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; %6 = LDtocL @ga, killed %5 :: (load (s64) from got)
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; %7 = LWZ 0, %6 :: (volatile dereferenceable load (s32) from @ga)
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; %8 = ADDIStocHA8 %x2, @gb
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; %9 = LDtocL @gb, killed %8 :: (load (s64) from got)
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; %10 = LWZ 0, killed %9 :: (volatile dereferenceable load (s32) from @gb)
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; %0 = LWZ 0, %6 :: (volatile dereferenceable load (s32) from @ga)
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; %11 = CMPW killed %7, killed %10
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; BCC 44, killed %11, %bb.2.if.then
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; B %bb.3.if.end
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;
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; bb.2.if.then:
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; %1 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
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; ADJCALLSTACKDOWN 32, 0, implicit-def dead %r1, implicit %r1
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; %20 = COPY %x2
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; STD %20, 24, %x1 :: (store (s64) into stack + 24)
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; %21 = EXTSW_32_64 %1
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; %x3 = COPY %21
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; %x12 = COPY %4
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; MTCTR8 %4, implicit-def %ctr8
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; BCTRL8_LDinto_toc 24, %x1, csr_ppc64_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3
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; ADJCALLSTACKUP 32, 0, implicit-def dead %r1, implicit %r1
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; %22 = COPY %x3
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; %x3 = COPY %22
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; BLR8 implicit %lr8, implicit %rm, implicit %x3
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;
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; bb.3.if.end:
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; successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000)
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;
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; %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
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; %12 = ADDI %2, 1
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; %13 = ADDIStocHA8 %x2, @ga
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; %14 = LDtocL @ga, killed %13 :: (load (s64) from got)
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; STW killed %12, 0, %14 :: (volatile store (s32) into @ga)
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; %15 = LWZ 0, %14 :: (volatile dereferenceable load (s32) from @ga)
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; %16 = ADDIStocHA8 %x2, @gb
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; %17 = LDtocL @gb, killed %16 :: (load (s64) from got)
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; %18 = LWZ 0, killed %17 :: (volatile dereferenceable load (s32) from @gb)
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; %3 = LWZ 0, %14 :: (volatile dereferenceable load (s32) from @ga)
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; %19 = CMPW killed %15, killed %18
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; BCC 44, killed %19, %bb.2.if.then
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; B %bb.3.if.end
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@ga = external global i32, align 4
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@gb = external global i32, align 4
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define signext i32 @test(ptr nocapture %FP) local_unnamed_addr #0 {
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; CHECKLX-LABEL: test:
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; CHECKLX: # %bb.0: # %entry
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; CHECKLX-NEXT: mr 12, 3
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; CHECKLX-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECKLX-NEXT: addis 4, 2, .LC1@toc@ha
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; CHECKLX-NEXT: ld 3, .LC0@toc@l(3)
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; CHECKLX-NEXT: ld 5, .LC1@toc@l(4)
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; CHECKLX-NEXT: lwz 6, 0(3)
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; CHECKLX-NEXT: .p2align 5
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; CHECKLX-NEXT: .LBB0_1: # %if.end
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; CHECKLX-NEXT: #
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; CHECKLX-NEXT: lwz 7, 0(5)
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; CHECKLX-NEXT: lwz 4, 0(3)
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; CHECKLX-NEXT: cmpw 6, 7
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; CHECKLX-NEXT: bgt 0, .LBB0_3
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; CHECKLX-NEXT: # %bb.2: # %if.end
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; CHECKLX-NEXT: #
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; CHECKLX-NEXT: addi 4, 4, 1
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; CHECKLX-NEXT: stw 4, 0(3)
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; CHECKLX-NEXT: lwz 6, 0(3)
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; CHECKLX-NEXT: b .LBB0_1
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; CHECKLX-NEXT: .LBB0_3: # %if.then
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; CHECKLX-NEXT: mflr 0
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; CHECKLX-NEXT: stdu 1, -32(1)
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; CHECKLX-NEXT: std 2, 24(1)
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; CHECKLX-NEXT: std 0, 48(1)
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; CHECKLX-NEXT: .cfi_def_cfa_offset 32
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; CHECKLX-NEXT: .cfi_offset lr, 16
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; CHECKLX-NEXT: mtctr 12
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; CHECKLX-NEXT: extsw 3, 4
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; CHECKLX-NEXT: bctrl
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; CHECKLX-NEXT: ld 2, 24(1)
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; CHECKLX-NEXT: addi 1, 1, 32
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; CHECKLX-NEXT: ld 0, 16(1)
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; CHECKLX-NEXT: mtlr 0
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; CHECKLX-NEXT: blr
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;
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; CHECKAIX-LABEL: test:
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; CHECKAIX: # %bb.0: # %entry
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; CHECKAIX-NEXT: ld 5, L..C0(2) # @ga
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; CHECKAIX-NEXT: ld 6, L..C1(2) # @gb
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; CHECKAIX-NEXT: L..BB0_1: # %if.end
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; CHECKAIX-NEXT: #
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; CHECKAIX-NEXT: lwz 4, 0(5)
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; CHECKAIX-NEXT: lwz 7, 0(6)
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; CHECKAIX-NEXT: cmpw 4, 7
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; CHECKAIX-NEXT: lwz 4, 0(5)
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; CHECKAIX-NEXT: bgt 0, L..BB0_3
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; CHECKAIX-NEXT: # %bb.2: # %if.end
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; CHECKAIX-NEXT: #
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; CHECKAIX-NEXT: addi 4, 4, 1
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; CHECKAIX-NEXT: stw 4, 0(5)
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; CHECKAIX-NEXT: b L..BB0_1
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; CHECKAIX-NEXT: L..BB0_3: # %if.then
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; CHECKAIX-NEXT: mflr 0
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; CHECKAIX-NEXT: stdu 1, -112(1)
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; CHECKAIX-NEXT: ld 5, 0(3)
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; CHECKAIX-NEXT: std 0, 128(1)
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; CHECKAIX-NEXT: ld 11, 16(3)
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; CHECKAIX-NEXT: std 2, 40(1)
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; CHECKAIX-NEXT: ld 2, 8(3)
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; CHECKAIX-NEXT: extsw 3, 4
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; CHECKAIX-NEXT: mtctr 5
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; CHECKAIX-NEXT: bctrl
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; CHECKAIX-NEXT: ld 2, 40(1)
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; CHECKAIX-NEXT: addi 1, 1, 112
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; CHECKAIX-NEXT: ld 0, 16(1)
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; CHECKAIX-NEXT: mtlr 0
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; CHECKAIX-NEXT: blr
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;
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; CHECKAIX32-LABEL: test:
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; CHECKAIX32: # %bb.0: # %entry
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; CHECKAIX32-NEXT: lwz 5, L..C0(2) # @ga
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; CHECKAIX32-NEXT: lwz 6, L..C1(2) # @gb
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; CHECKAIX32-NEXT: L..BB0_1: # %if.end
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; CHECKAIX32-NEXT: #
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; CHECKAIX32-NEXT: lwz 4, 0(5)
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; CHECKAIX32-NEXT: lwz 7, 0(6)
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; CHECKAIX32-NEXT: cmpw 4, 7
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; CHECKAIX32-NEXT: lwz 4, 0(5)
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; CHECKAIX32-NEXT: bgt 0, L..BB0_3
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; CHECKAIX32-NEXT: # %bb.2: # %if.end
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; CHECKAIX32-NEXT: #
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; CHECKAIX32-NEXT: addi 4, 4, 1
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; CHECKAIX32-NEXT: stw 4, 0(5)
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; CHECKAIX32-NEXT: b L..BB0_1
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; CHECKAIX32-NEXT: L..BB0_3: # %if.then
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; CHECKAIX32-NEXT: mflr 0
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; CHECKAIX32-NEXT: stwu 1, -64(1)
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; CHECKAIX32-NEXT: lwz 5, 0(3)
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; CHECKAIX32-NEXT: stw 0, 72(1)
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; CHECKAIX32-NEXT: stw 2, 20(1)
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; CHECKAIX32-NEXT: mtctr 5
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; CHECKAIX32-NEXT: lwz 11, 8(3)
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; CHECKAIX32-NEXT: lwz 2, 4(3)
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; CHECKAIX32-NEXT: mr 3, 4
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; CHECKAIX32-NEXT: bctrl
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; CHECKAIX32-NEXT: lwz 2, 20(1)
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; CHECKAIX32-NEXT: addi 1, 1, 64
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; CHECKAIX32-NEXT: lwz 0, 8(1)
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; CHECKAIX32-NEXT: mtlr 0
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; CHECKAIX32-NEXT: blr
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entry:
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%0 = load volatile i32, ptr @ga, align 4
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%1 = load volatile i32, ptr @gb, align 4
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%cmp1 = icmp sgt i32 %0, %1
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%2 = load volatile i32, ptr @ga, align 4
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %if.end, %entry
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%.lcssa = phi i32 [ %2, %entry ], [ %6, %if.end ]
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%call = tail call signext i32 %FP(i32 signext %.lcssa) #1
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ret i32 %call
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if.end: ; preds = %entry, %if.end
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%3 = phi i32 [ %6, %if.end ], [ %2, %entry ]
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%inc = add nsw i32 %3, 1
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store volatile i32 %inc, ptr @ga, align 4
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%4 = load volatile i32, ptr @ga, align 4
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%5 = load volatile i32, ptr @gb, align 4
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%cmp = icmp sgt i32 %4, %5
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%6 = load volatile i32, ptr @ga, align 4
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br i1 %cmp, label %if.then, label %if.end
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}
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