c42f0a6e64
The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31) as artificial regs, similar to how X86 has done it. And emit store /reload instructions for the required halves. PR : https://github.com/llvm/llvm-project/issues/57307 Reviewed By: jhibbits Differential Revision: https://reviews.llvm.org/D152437
103 lines
3.0 KiB
LLVM
103 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpcspe -verify-machineinstrs < %s | FileCheck %s
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define void @baz() #0 {
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; CHECK-LABEL: baz:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stwu 1, -16(1)
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; CHECK-NEXT: stw 0, 20(1)
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; CHECK-NEXT: mtctr 3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %bb1
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; CHECK-NEXT: #
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; CHECK-NEXT: bdnz .LBB0_1
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; CHECK-NEXT: # %bb.2: # %bb8
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; CHECK-NEXT: bl wibble
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; CHECK-NEXT: lwz 0, 20(1)
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; CHECK-NEXT: addi 1, 1, 16
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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bb:
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br label %bb1
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bb1:
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%tmp = phi i32 [ %tmp6, %bb1 ], [ undef, %bb ]
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%tmp2 = phi i32 [ %tmp3, %bb1 ], [ undef, %bb ]
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%tmp3 = add nsw i32 %tmp2, 1
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%tmp4 = sitofp i32 %tmp to double
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%tmp5 = tail call double @llvm.fmuladd.f64(double 0.000000e+00, double -0.000000e+00, double %tmp4)
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%tmp6 = fptosi double %tmp5 to i32
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%tmp7 = icmp eq i32 %tmp2, 0
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br i1 %tmp7, label %bb8, label %bb1
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bb8:
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call void @wibble(i32 %tmp6)
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ret void
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}
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define void @wombat() #0 {
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; CHECK-LABEL: wombat:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stwu 1, -48(1)
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; CHECK-NEXT: li 3, .LCPI1_0@l
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; CHECK-NEXT: li 5, .LCPI1_1@l
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; CHECK-NEXT: lis 4, .LCPI1_0@ha
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; CHECK-NEXT: lis 6, .LCPI1_1@ha
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; CHECK-NEXT: stw 0, 52(1)
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; CHECK-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
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; CHECK-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
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; CHECK-NEXT: evlddx 30, 4, 3
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; CHECK-NEXT: # implicit-def: $r3
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; CHECK-NEXT: evlddx 29, 6, 5
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; CHECK-NEXT: stw 28, 32(1) # 4-byte Folded Spill
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; CHECK-NEXT: # implicit-def: $r28
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB1_1: # %bb1
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; CHECK-NEXT: #
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; CHECK-NEXT: efdcfsi 8, 3
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; CHECK-NEXT: evmergehi 3, 30, 30
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; CHECK-NEXT: evmergehi 5, 29, 29
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; CHECK-NEXT: mr 4, 30
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; CHECK-NEXT: mr 6, 29
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; CHECK-NEXT: evmergehi 7, 8, 8
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; CHECK-NEXT: bl fma
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; CHECK-NEXT: evmergelo 3, 3, 4
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; CHECK-NEXT: addi 28, 28, -1
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; CHECK-NEXT: cmplwi 28, 0
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; CHECK-NEXT: efdctsiz 3, 3
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; CHECK-NEXT: bc 12, 1, .LBB1_1
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; CHECK-NEXT: # %bb.2: # %bb8
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; CHECK-NEXT: bl wibble
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; CHECK-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
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; CHECK-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
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; CHECK-NEXT: lwz 28, 32(1) # 4-byte Folded Reload
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; CHECK-NEXT: lwz 0, 52(1)
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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bb:
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br label %bb1
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bb1:
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%tmp = phi i32 [ %tmp6, %bb1 ], [ undef, %bb ]
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%tmp2 = phi i32 [ %tmp3, %bb1 ], [ undef, %bb ]
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%tmp3 = add nsw i32 %tmp2, 1
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%tmp4 = sitofp i32 %tmp to double
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%tmp5 = tail call double @llvm.fma.f64(double 0.000000e+00, double -0.000000e+00, double %tmp4)
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%tmp6 = fptosi double %tmp5 to i32
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%tmp7 = icmp eq i32 %tmp2, 0
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br i1 %tmp7, label %bb8, label %bb1
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bb8:
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call void @wibble(i32 %tmp6)
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ret void
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}
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declare void @wibble(i32)
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declare double @llvm.fmuladd.f64(double, double, double)
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declare double @llvm.fma.f64(double, double, double)
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attributes #0 = { nounwind }
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