67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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;; Types:
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; CHECK-DAG: %[[#I32:]] = OpTypeInt 32
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; CHECK-DAG: %[[#F32:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#FNI32:]] = OpTypeFunction %[[#I32]] %[[#I32]]
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; CHECK-DAG: %[[#FNF32:]] = OpTypeFunction %[[#F32]] %[[#F32]]
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;; Function declarations:
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; CHECK: %[[#ANON0:]] = OpFunction %[[#I32]] None %[[#FNI32]]
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; CHECK-NEXT: OpFunctionParameter %[[#I32]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: OpReturnValue
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; CHECK-NEXT: OpFunctionEnd
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define internal spir_func i32 @0(i32 %a) {
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ret i32 %a
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}
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; CHECK: %[[#ANON1:]] = OpFunction %[[#F32]] None %[[#FNF32]]
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; CHECK-NEXT: OpFunctionParameter %[[#F32]]
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; CHECK-NEXT: OpLabel
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; CHECK-NEXT: OpReturnValue
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; CHECK-NEXT: OpFunctionEnd
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define internal spir_func float @1(float %a) {
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ret float %a
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}
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;; Calls:
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; CHECK: OpFunctionCall %[[#I32]] %[[#ANON0]]
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; CHECK: OpFunctionCall %[[#F32]] %[[#ANON1]]
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define spir_kernel void @foo(i32 %a) {
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%call1 = call spir_func i32 @0(i32 %a)
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%b = sitofp i32 %a to float
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%call2 = call spir_func float @1(float %b)
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ret void
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}
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