67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
87 lines
1.9 KiB
LLVM
87 lines
1.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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;; FIXME: Are there any attributes that would make the IR invalid for SPIR-V?
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;; Names:
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; CHECK-DAG: OpName %[[#FN1:]] "fn1"
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; CHECK-DAG: OpName %[[#FN2:]] "fn2"
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; CHECK-DAG: OpName %[[#FN3:]] "fn3"
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; CHECK-DAG: OpName %[[#FN4:]] "fn4"
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; CHECK-DAG: OpName %[[#FN5:]] "fn5"
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; CHECK-DAG: OpName %[[#FN6:]] "fn6"
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; CHECK-DAG: OpName %[[#FN7:]] "fn7"
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; CHECK-DAG: OpName %[[#FN8:]] "fn8"
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; CHECK-DAG: OpName %[[#FN9:]] "fn9"
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;; Types:
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; CHECK: %[[#VOID:]] = OpTypeVoid
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; CHECK: %[[#FN:]] = OpTypeFunction %[[#VOID]]
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;; Functions:
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define void @fn1() noinline {
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ret void
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}
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; CHECK: %[[#FN1]] = OpFunction %[[#VOID]] DontInline %[[#FN]]
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; CHECK-NOT: OpFunctionParameter
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; CHECK: OpFunctionEnd
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attributes #0 = { noinline }
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define void @fn2() #0 {
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ret void
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}
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; CHECK: %[[#FN2]] = OpFunction %[[#VOID]] DontInline %[[#FN]]
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; CHECK: OpFunctionEnd
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define void @fn3() alwaysinline {
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ret void
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}
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; CHECK: %[[#FN3]] = OpFunction %[[#VOID]] Inline %[[#FN]]
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; CHECK: OpFunctionEnd
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;; NOTE: inlinehint is not an actual requirement.
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define void @fn4() inlinehint {
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ret void
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}
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; CHECK: %[[#FN4]] = OpFunction %[[#VOID]] None %[[#FN]]
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; CHECK: OpFunctionEnd
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define void @fn5() readnone {
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ret void
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}
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; CHECK: %[[#FN5]] = OpFunction %[[#VOID]] Pure %[[#FN]]
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; CHECK: OpFunctionEnd
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define void @fn6() memory(none) {
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ret void
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}
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; CHECK: %[[#FN6]] = OpFunction %[[#VOID]] Pure %[[#FN]]
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; CHECK: OpFunctionEnd
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define void @fn7() readonly {
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ret void
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}
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; CHECK: %[[#FN7]] = OpFunction %[[#VOID]] Const %[[#FN]]
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; CHECK: OpFunctionEnd
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define void @fn8() memory(read) {
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ret void
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}
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; CHECK: %[[#FN8]] = OpFunction %[[#VOID]] Const %[[#FN]]
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; CHECK: OpFunctionEnd
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define void @fn9() alwaysinline readnone {
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ret void
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}
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; CHECK: %[[#FN9]] = OpFunction %[[#VOID]] Inline|Pure %[[#FN]]
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; CHECK: OpFunctionEnd
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