67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[#VOID:]] = OpTypeVoid
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; CHECK-DAG: %[[#FLOAT:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#UCHAR:]] = OpTypeInt 8 0
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; CHECK-DAG: %[[#UINT:]] = OpTypeInt 32 0
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; CHECK-DAG: %[[#STRUCT_S:]] = OpTypeStruct %[[#FLOAT]] %[[#UCHAR]] %[[#UINT]]
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; CHECK-DAG: %[[#PTR_STRUCT_S:]] = OpTypePointer Function %[[#STRUCT_S]]
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; CHECK-DAG: %[[#FUNC_TYPE_K:]] = OpTypeFunction %[[#VOID]] %[[#PTR_STRUCT_S]]
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; CHECK-DAG: %[[#FUNC_TYPE_H:]] = OpTypeFunction %[[#UINT]] %[[#PTR_STRUCT_S]]
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; CHECK: %[[#]] = OpFunction %[[#VOID]] None %[[#FUNC_TYPE_K]]
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; CHECK: %[[#]] = OpFunctionParameter %[[#PTR_STRUCT_S]]
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; CHECK: %[[#]] = OpFunction %[[#UINT]] None %[[#FUNC_TYPE_H]]
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; CHECK: %[[#]] = OpFunctionParameter %[[#PTR_STRUCT_S]]
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%struct.s = type { float, i8, i32 }
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define spir_kernel void @k(ptr noundef byval(%struct.s) align 4 %x) {
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entry:
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%c = getelementptr inbounds %struct.s, ptr %x, i32 0, i32 2
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%l = load i32, ptr %c, align 4
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%add = add nsw i32 %l, 1
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%c1 = getelementptr inbounds %struct.s, ptr %x, i32 0, i32 2
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store i32 %add, ptr %c1, align 4
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ret void
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}
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define spir_func i32 @h(ptr noundef byval(%struct.s) align 4 %x) {
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entry:
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%c = getelementptr inbounds %struct.s, ptr %x, i32 0, i32 2
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%l = load i32, ptr %c, align 4
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%add = add nsw i32 %l, 1
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ret i32 %add
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}
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