67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
65 lines
2.1 KiB
LLVM
65 lines
2.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 0
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; CHECK-DAG: %[[#PTR1:]] = OpTypePointer Function %[[#INT]]
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; CHECK-DAG: %[[#ARG:]] = OpFunctionParameter %[[#PTR1]]
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define spir_kernel void @test1(ptr addrspace(0) %arg1) !kernel_arg_addr_space !1 !kernel_arg_type !2 {
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%a = getelementptr inbounds i32, ptr addrspace(0) %arg1, i32 2
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ret void
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}
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!1 = !{i32 0}
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!2 = !{!"int*"}
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; CHECK-DAG: %[[#PTR2:]] = OpTypePointer CrossWorkgroup %[[#INT]]
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; CHECK-DAG: %[[#ARG:]] = OpFunctionParameter %[[#PTR2]]
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define spir_kernel void @test2(ptr addrspace(1) %arg1) !kernel_arg_addr_space !3 !kernel_arg_type !2 {
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%a = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 2
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ret void
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}
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!3 = !{i32 1}
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; CHECK-DAG: %[[#PTR3:]] = OpTypePointer UniformConstant %[[#INT]]
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; CHECK-DAG: %[[#ARG:]] = OpFunctionParameter %[[#PTR3]]
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define spir_kernel void @test3(ptr addrspace(2) %arg1) !kernel_arg_addr_space !4 !kernel_arg_type !2 {
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%a = getelementptr inbounds i32, ptr addrspace(2) %arg1, i32 2
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ret void
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}
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!4 = !{i32 2}
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; CHECK-DAG: %[[#PTR4:]] = OpTypePointer Workgroup %[[#INT]]
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; CHECK-DAG: %[[#ARG:]] = OpFunctionParameter %[[#PTR4]]
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define spir_kernel void @test4(ptr addrspace(3) %arg1) !kernel_arg_addr_space !5 !kernel_arg_type !2 {
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%a = getelementptr inbounds i32, ptr addrspace(3) %arg1, i32 2
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ret void
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}
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!5 = !{i32 3}
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; CHECK-DAG: %[[#PTR5:]] = OpTypePointer Generic %[[#INT]]
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; CHECK-DAG: %[[#ARG:]] = OpFunctionParameter %[[#PTR5]]
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define spir_kernel void @test5(ptr addrspace(4) %arg1) !kernel_arg_addr_space !6 !kernel_arg_type !2 {
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%a = getelementptr inbounds i32, ptr addrspace(4) %arg1, i32 2
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ret void
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}
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!6 = !{i32 4}
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; CHECK-DAG: %[[#PTR6:]] = OpTypePointer Input %[[#INT]]
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; CHECK-DAG: %[[#ARG:]] = OpFunctionParameter %[[#PTR6]]
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define spir_kernel void @test6(ptr addrspace(7) %arg1) !kernel_arg_addr_space !7 !kernel_arg_type !2 {
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%a = getelementptr inbounds i32, ptr addrspace(7) %arg1, i32 2
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ret void
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}
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!7 = !{i32 7}
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