f9c98068c8
This PR contains changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. This potentially helps to detect previously missed flaws in code emission and harden the test suite. As a measure of correctness and usefulness of this PR we may use a mode with expensive checks set on, and MachineVerifier reports problems in the test suite. In order to satisfy Machine Verifier requirements to MIR correctness not only a rework of usage of virtual registers' types and classes is required, but also corrections into pre-legalizer and instruction selection logics. Namely, the following changes are introduced: * scalar virtual registers have proper bit width, * detect register class by SPIR-V type, * add a superclass for id virtual register classes, * fix Tablegen rules used for instruction selection, * fixes of minor existed issues (missed flag for proper representation of a null constant for OpenCL vs. HLSL, wrong usage of integer virtual registers as a synonym of any non-type virtual register).
65 lines
2.6 KiB
LLVM
65 lines
2.6 KiB
LLVM
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-SPIRV: OpName %[[#r1:]] "r1"
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; CHECK-SPIRV: OpName %[[#r2:]] "r2"
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; CHECK-SPIRV: OpName %[[#r3:]] "r3"
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; CHECK-SPIRV: OpName %[[#r4:]] "r4"
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; CHECK-SPIRV: OpName %[[#r5:]] "r5"
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; CHECK-SPIRV: OpName %[[#r6:]] "r6"
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; CHECK-SPIRV: OpName %[[#r7:]] "r7"
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; CHECK-SPIRV: OpName %[[#r1d:]] "r1"
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; CHECK-SPIRV: OpName %[[#r2d:]] "r2"
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; CHECK-SPIRV: OpName %[[#r3d:]] "r3"
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; CHECK-SPIRV: OpName %[[#r4d:]] "r4"
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; CHECK-SPIRV: OpName %[[#r5d:]] "r5"
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; CHECK-SPIRV: OpName %[[#r6d:]] "r6"
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; CHECK-SPIRV: OpName %[[#r7d:]] "r7"
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; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
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; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
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; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
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; CHECK-SPIRV-DAG: OpDecorate %[[#r4]] FPFastMathMode NSZ
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; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
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; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
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; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
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; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
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; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64
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; CHECK-SPIRV: %[[#r1]] = OpFAdd %[[#float]]
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; CHECK-SPIRV: %[[#r2]] = OpFAdd %[[#float]]
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; CHECK-SPIRV: %[[#r3]] = OpFAdd %[[#float]]
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; CHECK-SPIRV: %[[#r4]] = OpFAdd %[[#float]]
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; CHECK-SPIRV: %[[#r5]] = OpFAdd %[[#float]]
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; CHECK-SPIRV: %[[#r6]] = OpFAdd %[[#float]]
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; CHECK-SPIRV: %[[#r7]] = OpFAdd %[[#float]]
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define spir_kernel void @testFAdd_float(float %a, float %b) {
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entry:
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%r1 = fadd float %a, %b
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%r2 = fadd nnan float %a, %b
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%r3 = fadd ninf float %a, %b
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%r4 = fadd nsz float %a, %b
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%r5 = fadd arcp float %a, %b
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%r6 = fadd fast float %a, %b
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%r7 = fadd nnan ninf float %a, %b
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ret void
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}
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; CHECK-SPIRV: %[[#r1d]] = OpFAdd %[[#double]]
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; CHECK-SPIRV: %[[#r2d]] = OpFAdd %[[#double]]
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; CHECK-SPIRV: %[[#r3d]] = OpFAdd %[[#double]]
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; CHECK-SPIRV: %[[#r4d]] = OpFAdd %[[#double]]
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; CHECK-SPIRV: %[[#r5d]] = OpFAdd %[[#double]]
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; CHECK-SPIRV: %[[#r6d]] = OpFAdd %[[#double]]
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; CHECK-SPIRV: %[[#r7d]] = OpFAdd %[[#double]]
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define spir_kernel void @testFAdd_double(double %a, double %b) {
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entry:
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%r1 = fadd double %a, %b
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%r2 = fadd nnan double %a, %b
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%r3 = fadd ninf double %a, %b
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%r4 = fadd nsz double %a, %b
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%r5 = fadd arcp double %a, %b
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%r6 = fadd fast double %a, %b
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%r7 = fadd nnan ninf double %a, %b
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ret void
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}
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