1d1893097a
The usage of FP Load and Test instructions as a comparison against zero with the assumption that the dest reg will always reflect the source reg is actually incorrect: Unfortunately, a SNaN will be converted to a QNaN, so the instruction may actually change the value as opposed to being a pure register move with a test. This patch - changes instruction selection to always emit FP LT with a scratch def reg, which will typically be allocated to the same reg if dead. - Removes the conversions into FP LT in SystemZElimcompare.
95 lines
2.4 KiB
LLVM
95 lines
2.4 KiB
LLVM
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Check comparisons with zero. If the tested value is live after the
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; comparison, load and test cannot be used to the same register.
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; Compared value is used afterwards.
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define i64 @f1(i64 %a, i64 %b, float %V, ptr %dst) {
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; CHECK-LABEL: f1:
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; CHECK: ltebr %f1, %f0
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%cond = fcmp oeq float %V, 0.0
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%res = select i1 %cond, i64 %a, i64 %b
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store volatile float %V, ptr %dst
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ret i64 %res
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}
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define i64 @f1m(i64 %a, i64 %b, float %V, ptr %dst) {
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; CHECK-LABEL: f1m:
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; CHECK: ltebr %f1, %f0
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%cond = fcmp oeq float %V, -0.0
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%res = select i1 %cond, i64 %a, i64 %b
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store volatile float %V, ptr %dst
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ret i64 %res
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}
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; Value only used in comparison.
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define i64 @f2(i64 %a, i64 %b, float %V) {
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; CHECK-LABEL: f2:
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; CHECK: ltebr %f0, %f0
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%cond = fcmp oeq float %V, 0.0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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define i64 @f2m(i64 %a, i64 %b, float %V) {
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; CHECK-LABEL: f2m:
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; CHECK: ltebr %f0, %f0
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%cond = fcmp oeq float %V, -0.0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Same for double
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define i64 @f3(i64 %a, i64 %b, double %V, ptr %dst) {
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; CHECK-LABEL: f3:
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; CHECK: ltdbr %f1, %f0
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%cond = fcmp oeq double %V, 0.0
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%res = select i1 %cond, i64 %a, i64 %b
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store volatile double %V, ptr %dst
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ret i64 %res
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}
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define i64 @f3m(i64 %a, i64 %b, double %V, ptr %dst) {
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; CHECK-LABEL: f3m:
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; CHECK: ltdbr %f1, %f0
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%cond = fcmp oeq double %V, -0.0
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%res = select i1 %cond, i64 %a, i64 %b
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store volatile double %V, ptr %dst
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ret i64 %res
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}
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define i64 @f4(i64 %a, i64 %b, double %V) {
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; CHECK-LABEL: f4:
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; CHECK: ltdbr %f0, %f0
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%cond = fcmp oeq double %V, 0.0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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define i64 @f4m(i64 %a, i64 %b, double %V) {
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; CHECK-LABEL: f4m:
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; CHECK: ltdbr %f0, %f0
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%cond = fcmp oeq double %V, -0.0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Same for fp128
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define i64 @f5(i64 %a, i64 %b, fp128 %V, ptr %dst) {
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; CHECK-LABEL: f5:
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; CHECK: ltxbr %f1, %f0
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%cond = fcmp oeq fp128 %V, 0xL00000000000000008000000000000000
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%res = select i1 %cond, i64 %a, i64 %b
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store volatile fp128 %V, ptr %dst
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ret i64 %res
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}
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define i64 @f6(i64 %a, i64 %b, fp128 %V) {
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; CHECK-LABEL: f6:
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; CHECK: ltxbr %f0, %f0
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%cond = fcmp oeq fp128 %V, 0xL00000000000000008000000000000000
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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