a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
211 lines
5.3 KiB
LLVM
211 lines
5.3 KiB
LLVM
; Test 64-bit signed division and remainder when the divisor is
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; a signed-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
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declare i64 @foo()
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; Test register division. The result is in the second of the two registers.
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define void @f1(i64 %dummy, i64 %a, i32 %b, ptr %dest) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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store i64 %div, ptr %dest
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ret void
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}
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; Test register remainder. The result is in the first of the two registers.
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define void @f2(i64 %dummy, i64 %a, i32 %b, ptr %dest) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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store i64 %rem, ptr %dest
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ret void
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}
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; Test that division and remainder use a single instruction.
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define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK: ogr %r3, %r2
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; CHECK: lgr %r2, %r3
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; CHECK: br %r14
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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%rem = srem i64 %a, %bext
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Test register division when the dividend is zero rather than sign extended.
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; We can't use dsgfr here
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define void @f4(i64 %dummy, i64 %a, i32 %b, ptr %dest) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: dsgfr
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%div = sdiv i64 %a, %bext
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store i64 %div, ptr %dest
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ret void
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}
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; ...likewise remainder.
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define void @f5(i64 %dummy, i64 %a, i32 %b, ptr %dest) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: dsgfr
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%rem = srem i64 %a, %bext
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store i64 %rem, ptr %dest
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ret void
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}
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; Test memory division with no displacement.
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define void @f6(i64 %dummy, i64 %a, ptr %src, ptr %dest) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%b = load i32, ptr %src
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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store i64 %div, ptr %dest
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ret void
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}
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; Test memory remainder with no displacement.
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define void @f7(i64 %dummy, i64 %a, ptr %src, ptr %dest) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%b = load i32, ptr %src
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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store i64 %rem, ptr %dest
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ret void
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}
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; Test both memory division and memory remainder.
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define i64 @f8(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK-NOT: {{dsgf|dsgfr}}
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; CHECK: ogr %r3, %r2
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; CHECK: lgr %r2, %r3
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; CHECK: br %r14
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%b = load i32, ptr %src
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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%rem = srem i64 %a, %bext
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Check the high end of the DSGF range.
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define i64 @f9(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f9:
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; CHECK: dsgf %r2, 524284(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131071
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%b = load i32, ptr %ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f10(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r4, 524288
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131072
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%b = load i32, ptr %ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the high end of the negative aligned DSGF range.
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define i64 @f11(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f11:
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; CHECK: dsgf %r2, -4(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -1
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%b = load i32, ptr %ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the low end of the DSGF range.
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define i64 @f12(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f12:
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; CHECK: dsgf %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131072
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%b = load i32, ptr %ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f13(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f13:
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; CHECK: agfi %r4, -524292
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131073
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%b = load i32, ptr %ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check that DSGF allows an index.
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define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f14:
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; CHECK: dsgf %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to ptr
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%b = load i32, ptr %ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Make sure that we still use DSGFR rather than DSGR in cases where
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; a load and division cannot be combined.
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define void @f15(ptr %dest, ptr %src) {
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; CHECK-LABEL: f15:
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; CHECK: l [[B:%r[0-9]+]], 0(%r3)
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; CHECK: brasl %r14, foo@PLT
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; CHECK: lgr %r1, %r2
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; CHECK: dsgfr %r0, [[B]]
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; CHECK: br %r14
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%b = load i32, ptr %src
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%a = call i64 @foo()
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%ext = sext i32 %b to i64
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%div = sdiv i64 %a, %ext
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store i64 %div, ptr %dest
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ret void
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}
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