a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
215 lines
5.5 KiB
LLVM
215 lines
5.5 KiB
LLVM
; Testg 64-bit unsigned division and remainder.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
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declare i64 @foo()
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; Testg register division. The result is in the second of the two registers.
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define void @f1(i64 %dummy, i64 %a, i64 %b, ptr %dest) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lghi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlgr %r2, %r4
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%div = udiv i64 %a, %b
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store i64 %div, ptr %dest
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ret void
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}
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; Testg register remainder. The result is in the first of the two registers.
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define void @f2(i64 %dummy, i64 %a, i64 %b, ptr %dest) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lghi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlgr %r2, %r4
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%rem = urem i64 %a, %b
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store i64 %rem, ptr %dest
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ret void
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}
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; Testg that division and remainder use a single instruction.
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define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lghi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlgr %r2, %r4
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; CHECK-NOT: dlgr
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%div = udiv i64 %a, %b
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%rem = urem i64 %a, %b
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Testg memory division with no displacement.
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define void @f4(i64 %dummy, i64 %a, ptr %src, ptr %dest) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lghi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlg %r2, 0(%r4)
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%b = load i64, ptr %src
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%div = udiv i64 %a, %b
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store i64 %div, ptr %dest
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ret void
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}
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; Testg memory remainder with no displacement.
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define void @f5(i64 %dummy, i64 %a, ptr %src, ptr %dest) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lghi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlg %r2, 0(%r4)
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%b = load i64, ptr %src
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%rem = urem i64 %a, %b
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store i64 %rem, ptr %dest
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ret void
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}
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; Testg both memory division and memory remainder.
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define i64 @f6(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: %r3
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; CHECK: {{llill|lghi}} %r2, 0
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; CHECK-NOT: %r3
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; CHECK: dlg %r2, 0(%r4)
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; CHECK-NOT: {{dlg|dlgr}}
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%b = load i64, ptr %src
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%div = udiv i64 %a, %b
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%rem = urem i64 %a, %b
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Check the high end of the DLG range.
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define i64 @f7(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: dlg %r2, 524280(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64, ptr %src, i64 65535
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%b = load i64, ptr %ptr
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f8(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r4, 524288
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; CHECK: dlg %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64, ptr %src, i64 65536
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%b = load i64, ptr %ptr
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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; Check the high end of the negative aligned DLG range.
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define i64 @f9(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f9:
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; CHECK: dlg %r2, -8(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64, ptr %src, i64 -1
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%b = load i64, ptr %ptr
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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; Check the low end of the DLG range.
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define i64 @f10(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f10:
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; CHECK: dlg %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64, ptr %src, i64 -65536
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%b = load i64, ptr %ptr
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f11(i64 %dummy, i64 %a, ptr %src) {
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; CHECK-LABEL: f11:
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; CHECK: agfi %r4, -524296
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; CHECK: dlg %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64, ptr %src, i64 -65537
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%b = load i64, ptr %ptr
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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; Check that DLG allows an index.
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define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f12:
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; CHECK: dlg %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to ptr
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%b = load i64, ptr %ptr
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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; Check that divisions of spilled values can use DLG rather than DLGR.
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define i64 @f13(ptr %ptr0) {
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; CHECK-LABEL: f13:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: dlg {{%r[0-9]+}}, 160(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i64, ptr %ptr0, i64 2
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%ptr2 = getelementptr i64, ptr %ptr0, i64 4
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%ptr3 = getelementptr i64, ptr %ptr0, i64 6
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%ptr4 = getelementptr i64, ptr %ptr0, i64 8
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%ptr5 = getelementptr i64, ptr %ptr0, i64 10
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%ptr6 = getelementptr i64, ptr %ptr0, i64 12
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%ptr7 = getelementptr i64, ptr %ptr0, i64 14
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%ptr8 = getelementptr i64, ptr %ptr0, i64 16
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%ptr9 = getelementptr i64, ptr %ptr0, i64 18
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%ptr10 = getelementptr i64, ptr %ptr0, i64 20
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%val0 = load i64, ptr %ptr0
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%val1 = load i64, ptr %ptr1
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%val2 = load i64, ptr %ptr2
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%val3 = load i64, ptr %ptr3
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%val4 = load i64, ptr %ptr4
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%val5 = load i64, ptr %ptr5
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%val6 = load i64, ptr %ptr6
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%val7 = load i64, ptr %ptr7
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%val8 = load i64, ptr %ptr8
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%val9 = load i64, ptr %ptr9
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%val10 = load i64, ptr %ptr10
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%ret = call i64 @foo()
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%div0 = udiv i64 %ret, %val0
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%div1 = udiv i64 %div0, %val1
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%div2 = udiv i64 %div1, %val2
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%div3 = udiv i64 %div2, %val3
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%div4 = udiv i64 %div3, %val4
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%div5 = udiv i64 %div4, %val5
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%div6 = udiv i64 %div5, %val6
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%div7 = udiv i64 %div6, %val7
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%div8 = udiv i64 %div7, %val8
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%div9 = udiv i64 %div8, %val9
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%div10 = udiv i64 %div9, %val10
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ret i64 %div10
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}
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