a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
205 lines
5.5 KiB
LLVM
205 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test i128 maximum on z13.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test with slt.
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define i128 @f1(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vecg %v1, %v0
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; CHECK-NEXT: je .LBB0_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jnl .LBB0_4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: vchlgs %v2, %v0, %v1
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; CHECK-NEXT: jl .LBB0_2
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp slt i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with sle.
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define i128 @f2(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vecg %v0, %v1
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; CHECK-NEXT: je .LBB1_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jl .LBB1_4
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB1_3:
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; CHECK-NEXT: vchlgs %v2, %v1, %v0
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; CHECK-NEXT: jnl .LBB1_2
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; CHECK-NEXT: .LBB1_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp sle i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with sgt.
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define i128 @f3(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vecg %v1, %v0
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; CHECK-NEXT: je .LBB2_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jnl .LBB2_4
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB2_3:
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; CHECK-NEXT: vchlgs %v2, %v0, %v1
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; CHECK-NEXT: jl .LBB2_2
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; CHECK-NEXT: .LBB2_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp sgt i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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; Test with sge.
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define i128 @f4(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vecg %v0, %v1
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; CHECK-NEXT: je .LBB3_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jl .LBB3_4
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB3_3:
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; CHECK-NEXT: vchlgs %v2, %v1, %v0
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; CHECK-NEXT: jnl .LBB3_2
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; CHECK-NEXT: .LBB3_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp sge i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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; Test with ult.
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define i128 @f5(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: veclg %v1, %v0
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; CHECK-NEXT: je .LBB4_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jnl .LBB4_4
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB4_3:
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; CHECK-NEXT: vchlgs %v2, %v0, %v1
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; CHECK-NEXT: jl .LBB4_2
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; CHECK-NEXT: .LBB4_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp ult i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with ule.
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define i128 @f6(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: veclg %v0, %v1
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; CHECK-NEXT: je .LBB5_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jl .LBB5_4
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB5_3:
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; CHECK-NEXT: vchlgs %v2, %v1, %v0
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; CHECK-NEXT: jnl .LBB5_2
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; CHECK-NEXT: .LBB5_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp ule i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val2, i128 %val1
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ret i128 %ret
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}
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; Test with ugt.
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define i128 @f7(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: veclg %v1, %v0
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; CHECK-NEXT: je .LBB6_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jnl .LBB6_4
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB6_3:
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; CHECK-NEXT: vchlgs %v2, %v0, %v1
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; CHECK-NEXT: jl .LBB6_2
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; CHECK-NEXT: .LBB6_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp ugt i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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; Test with uge.
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define i128 @f8(i128 %val1, i128 %val2) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: veclg %v0, %v1
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; CHECK-NEXT: je .LBB7_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: jl .LBB7_4
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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; CHECK-NEXT: .LBB7_3:
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; CHECK-NEXT: vchlgs %v2, %v1, %v0
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; CHECK-NEXT: jnl .LBB7_2
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; CHECK-NEXT: .LBB7_4:
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; CHECK-NEXT: vlr %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cmp = icmp uge i128 %val1, %val2
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%ret = select i1 %cmp, i128 %val1, i128 %val2
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ret i128 %ret
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}
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