a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
187 lines
5.3 KiB
LLVM
187 lines
5.3 KiB
LLVM
; Test additions between an i64 and a sign-extended i16 on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare i64 @foo()
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; Check AGH with no displacement.
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define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f1:
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; CHECK: agh %r3, 0(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%half = load i16, ptr %src
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the aligned AGH range.
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define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f4:
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; CHECK: agh %r3, 524286(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262143
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%half = load i16, ptr %ptr
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f5:
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; CHECK: agfi %r4, 524288
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; CHECK: agh %r3, 0(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262144
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%half = load i16, ptr %ptr
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the negative aligned AGH range.
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define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f6:
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; CHECK: agh %r3, -2(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -1
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%half = load i16, ptr %ptr
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the low end of the AGH range.
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define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f7:
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; CHECK: agh %r3, -524288(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262144
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%half = load i16, ptr %ptr
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r4, -524290
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; CHECK: agh %r3, 0(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262145
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%half = load i16, ptr %ptr
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check that AGH allows an index.
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define zeroext i1 @f9(i64 %src, i64 %index, i64 %a, ptr %res) {
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; CHECK-LABEL: f9:
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; CHECK: agh %r4, 524284({{%r3,%r2|%r2,%r3}})
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; CHECK-DAG: stg %r4, 0(%r5)
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; CHECK-DAG: lghi %r2, 0
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; CHECK-DAG: locghio %r2, 1
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to ptr
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%half = load i16, ptr %ptr
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f11(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f11:
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; CHECK: agh %r3, 0(%r4)
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; CHECK: stg %r3, 0(%r5)
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; CHECK: jgo foo@PLT
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; CHECK: br %r14
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%half = load i16, ptr %src
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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br i1 %obit, label %call, label %exit
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call:
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tail call i64 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f12(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f12:
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; CHECK: agh %r3, 0(%r4)
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; CHECK: stg %r3, 0(%r5)
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; CHECK: jgno foo@PLT
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; CHECK: br %r14
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%half = load i16, ptr %src
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%b = sext i16 %half to i64
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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br i1 %obit, label %exit, label %call
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call:
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tail call i64 @foo()
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br label %exit
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exit:
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ret void
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}
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declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
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