a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
266 lines
7.9 KiB
LLVM
266 lines
7.9 KiB
LLVM
; Test 64-bit addition in which the second operand is constant.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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declare i32 @foo()
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; Check additions of 1.
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define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f1:
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; CHECK: aghi %r3, 1
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the AGHI range.
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define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f2:
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; CHECK: aghi %r3, 32767
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 32767)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next value up, which must use AGFI instead.
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define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r3, 32768
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 32768)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the AGFI range.
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define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r3, 2147483647
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 2147483647)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next value up, which must be loaded into a register first.
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define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f5:
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; CHECK: llilh [[REG1:%r[0-9]+]], 32768
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; CHECK: agr [[REG1]], %r3
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; CHECK-DAG: stg [[REG1]], 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 2147483648)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the negative AGHI range.
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define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f6:
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; CHECK: aghi %r3, -1
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the low end of the AGHI range.
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define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f7:
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; CHECK: aghi %r3, -32768
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -32768)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next value down, which must use AGFI instead.
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define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r3, -32769
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -32769)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the low end of the AGFI range.
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define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r3, -2147483648
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -2147483648)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next value down, which can use register subtraction instead.
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define zeroext i1 @f10(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f10:
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; CHECK: llilf [[REG1:%r[0-9]+]], 2147483649
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; CHECK: sgr %r3, [[REG1]]
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -2147483649)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; We may be able to use LLILH instead of LLILF.
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define zeroext i1 @f11(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f11:
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; CHECK: llilh [[REG1:%r[0-9]+]], 32769
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; CHECK: sgr %r3, [[REG1]]
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -2147549184)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check low end of the LLILF/SGR range.
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define zeroext i1 @f12(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f12:
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; CHECK: llilf [[REG1:%r[0-9]+]], 4294967295
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; CHECK: sgr %r3, [[REG1]]
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; CHECK-DAG: stg %r3, 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -4294967295)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next value down, which must use register addition instead.
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define zeroext i1 @f13(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f13:
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; CHECK: llihf [[REG1:%r[0-9]+]], 4294967295
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; CHECK: agr [[REG1]], %r3
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; CHECK-DAG: stg [[REG1]], 0(%r4)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 -4294967296)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f14(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f14:
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; CHECK: aghi %r3, 1
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; CHECK: stg %r3, 0(%r4)
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; CHECK: {{jgo foo@PLT|bnor %r14}}
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; CHECK: {{br %r14|jg foo@PLT}}
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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br i1 %obit, label %call, label %exit
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f15(i64 %dummy, i64 %a, ptr %res) {
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; CHECK-LABEL: f15:
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; CHECK: aghi %r3, 1
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; CHECK: stg %r3, 0(%r4)
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; CHECK: {{jgno foo@PLT|bor %r14}}
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; CHECK: {{br %r14|jg foo@PLT}}
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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br i1 %obit, label %exit, label %call
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
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