a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
181 lines
4.7 KiB
LLVM
181 lines
4.7 KiB
LLVM
; Test subtractions of a zero-extended i32 from an i64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Check SLGFR.
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define i64 @f1(i64 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: slgfr %r2, %r3
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check SLGF with no displacement.
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define i64 @f2(i64 %a, ptr %src) {
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; CHECK-LABEL: f2:
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; CHECK: slgf %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i32, ptr %src
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the high end of the aligned SLGF range.
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define i64 @f3(i64 %a, ptr %src) {
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; CHECK-LABEL: f3:
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; CHECK: slgf %r2, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131071
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%b = load i32, ptr %ptr
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f4(i64 %a, ptr %src) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: slgf %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131072
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%b = load i32, ptr %ptr
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the high end of the negative aligned SLGF range.
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define i64 @f5(i64 %a, ptr %src) {
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; CHECK-LABEL: f5:
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; CHECK: slgf %r2, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -1
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%b = load i32, ptr %ptr
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the low end of the SLGF range.
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define i64 @f6(i64 %a, ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: slgf %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131072
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%b = load i32, ptr %ptr
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 %a, ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r3, -524292
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; CHECK: slgf %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 -131073
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%b = load i32, ptr %ptr
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check that SLGF allows an index.
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define i64 @f8(i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: slgf %r2, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to ptr
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%b = load i32, ptr %ptr
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%bext = zext i32 %b to i64
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%sub = sub i64 %a, %bext
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ret i64 %sub
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}
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; Check that subtractions of spilled values can use SLGF rather than SLGFR.
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define i64 @f9(ptr %ptr0) {
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; CHECK-LABEL: f9:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: slgf %r2, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32, ptr %ptr0, i64 2
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%ptr2 = getelementptr i32, ptr %ptr0, i64 4
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%ptr3 = getelementptr i32, ptr %ptr0, i64 6
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%ptr4 = getelementptr i32, ptr %ptr0, i64 8
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%ptr5 = getelementptr i32, ptr %ptr0, i64 10
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%ptr6 = getelementptr i32, ptr %ptr0, i64 12
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%ptr7 = getelementptr i32, ptr %ptr0, i64 14
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%ptr8 = getelementptr i32, ptr %ptr0, i64 16
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%ptr9 = getelementptr i32, ptr %ptr0, i64 18
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%val0 = load i32, ptr %ptr0
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%val1 = load i32, ptr %ptr1
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%val2 = load i32, ptr %ptr2
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%val3 = load i32, ptr %ptr3
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%val4 = load i32, ptr %ptr4
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%val5 = load i32, ptr %ptr5
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%val6 = load i32, ptr %ptr6
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%val7 = load i32, ptr %ptr7
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%val8 = load i32, ptr %ptr8
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%val9 = load i32, ptr %ptr9
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%frob0 = add i32 %val0, 100
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%frob1 = add i32 %val1, 100
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%frob2 = add i32 %val2, 100
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%frob3 = add i32 %val3, 100
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%frob4 = add i32 %val4, 100
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%frob5 = add i32 %val5, 100
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%frob6 = add i32 %val6, 100
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%frob7 = add i32 %val7, 100
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%frob8 = add i32 %val8, 100
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%frob9 = add i32 %val9, 100
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store i32 %frob0, ptr %ptr0
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store i32 %frob1, ptr %ptr1
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store i32 %frob2, ptr %ptr2
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store i32 %frob3, ptr %ptr3
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store i32 %frob4, ptr %ptr4
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store i32 %frob5, ptr %ptr5
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store i32 %frob6, ptr %ptr6
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store i32 %frob7, ptr %ptr7
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store i32 %frob8, ptr %ptr8
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store i32 %frob9, ptr %ptr9
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%ret = call i64 @foo()
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%ext0 = zext i32 %frob0 to i64
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%ext1 = zext i32 %frob1 to i64
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%ext2 = zext i32 %frob2 to i64
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%ext3 = zext i32 %frob3 to i64
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%ext4 = zext i32 %frob4 to i64
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%ext5 = zext i32 %frob5 to i64
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%ext6 = zext i32 %frob6 to i64
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%ext7 = zext i32 %frob7 to i64
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%ext8 = zext i32 %frob8 to i64
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%ext9 = zext i32 %frob9 to i64
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%sub0 = sub i64 %ret, %ext0
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%sub1 = sub i64 %sub0, %ext1
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%sub2 = sub i64 %sub1, %ext2
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%sub3 = sub i64 %sub2, %ext3
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%sub4 = sub i64 %sub3, %ext4
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%sub5 = sub i64 %sub4, %ext5
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%sub6 = sub i64 %sub5, %ext6
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%sub7 = sub i64 %sub6, %ext7
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%sub8 = sub i64 %sub7, %ext8
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%sub9 = sub i64 %sub8, %ext9
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ret i64 %sub9
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}
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