58a88001f3
This fixes the handling of subregister extract copies. This will allow AMDGPU to remove its implementation of shouldRewriteCopySrc, which exists as a 10 year old workaround to this bug. peephole-opt-fold-reg-sequence-subreg.mir will show the expected improvement once the custom implementation is removed. The copy coalescing processing here is overly abstracted from what's actually happening. Previously when visiting coalescable copy-like instructions, we would parse the sources one at a time and then pass the def of the root instruction into findNextSource. This means that the first thing the new ValueTracker constructed would do is getVRegDef to find the instruction we are currently processing. This adds an unnecessary step, placing a useless entry in the RewriteMap, and required skipping the no-op case where getNewSource would return the original source operand. This was a problem since in the case of a subregister extract, shouldRewriteCopySource would always say that it is useful to rewrite and the use-def chain walk would abort, returning the original operand. Move the process to start looking at the source operand to begin with. This does not fix the confused handling in the uncoalescable copy case which is proving to be more difficult. Some currently handled cases have multiple defs from a single source, and other handled cases have 0 input operands. It would be simpler if this was implemented with isCopyLikeInstr, rather than guessing at the operand structure as it does now. There are some improvements and some regressions. The regressions appear to be downstream issues for the most part. One of the uglier regressions is in PPC, where a sequence of insert_subrgs is used to build registers. I opened #125502 to use reg_sequence instead, which may help. The worst regression is an absurd SPARC testcase using a <251 x fp128>, which uses a very long chain of insert_subregs. We need improved subregister handling locally in PeepholeOptimizer, and other pasess like MachineCSE to fix some of the other regressions. We should handle subregister composes and folding more indexes into insert_subreg and reg_sequence.
330 lines
11 KiB
LLVM
330 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; Test 64-bit addition in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Check ALGR.
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define zeroext i1 @f1(i64 %dummy, i64 %a, i64 %b, ptr %res) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: algr %r3, %r4
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f2(i64 %dummy, i64 %a, i64 %b, ptr %res) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: algr %r3, %r4
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: jgnle foo@PLT
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; CHECK-NEXT: .LBB1_1: # %exit
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; CHECK-NEXT: br %r14
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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br i1 %obit, label %call, label %exit
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call:
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tail call i64 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f3(i64 %dummy, i64 %a, i64 %b, ptr %res) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: algr %r3, %r4
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: jgle foo@PLT
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; CHECK-NEXT: .LBB2_1: # %exit
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; CHECK-NEXT: br %r14
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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br i1 %obit, label %exit, label %call
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call:
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tail call i64 @foo()
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br label %exit
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exit:
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ret void
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}
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; Check ALG with no displacement.
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define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alg %r3, 0(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%b = load i64, ptr %src
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the aligned ALG range.
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define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alg %r3, 524280(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i64, ptr %src, i64 65535
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%b = load i64, ptr %ptr
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: agfi %r4, 524288
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; CHECK-NEXT: alg %r3, 0(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i64, ptr %src, i64 65536
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%b = load i64, ptr %ptr
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the high end of the negative aligned ALG range.
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define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alg %r3, -8(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i64, ptr %src, i64 -1
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%b = load i64, ptr %ptr
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the low end of the ALG range.
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define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alg %r3, -524288(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i64, ptr %src, i64 -65536
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%b = load i64, ptr %ptr
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: agfi %r4, -524296
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; CHECK-NEXT: alg %r3, 0(%r4)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%ptr = getelementptr i64, ptr %src, i64 -65537
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%b = load i64, ptr %ptr
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check that ALG allows an index.
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define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
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; CHECK-LABEL: f10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: alg %r4, 524280(%r3,%r2)
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
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; CHECK-NEXT: stg %r4, 0(%r5)
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; CHECK-NEXT: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524280
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%ptr = inttoptr i64 %add2 to ptr
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%b = load i64, ptr %ptr
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, ptr %res
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ret i1 %obit
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}
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; Check that additions of spilled values can use ALG rather than ALGR.
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define zeroext i1 @f11(ptr %ptr0) {
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; CHECK-LABEL: f11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
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; CHECK-NEXT: .cfi_offset %r6, -112
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; CHECK-NEXT: .cfi_offset %r7, -104
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; CHECK-NEXT: .cfi_offset %r8, -96
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; CHECK-NEXT: .cfi_offset %r9, -88
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; CHECK-NEXT: .cfi_offset %r10, -80
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r12, -64
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -176
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; CHECK-NEXT: .cfi_def_cfa_offset 336
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; CHECK-NEXT: lg %r7, 0(%r2)
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; CHECK-NEXT: lg %r6, 16(%r2)
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; CHECK-NEXT: lg %r13, 32(%r2)
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; CHECK-NEXT: lg %r12, 48(%r2)
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; CHECK-NEXT: lg %r8, 64(%r2)
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; CHECK-NEXT: lg %r9, 80(%r2)
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; CHECK-NEXT: lg %r10, 96(%r2)
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; CHECK-NEXT: lg %r11, 112(%r2)
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; CHECK-NEXT: mvc 160(8,%r15), 128(%r2) # 8-byte Folded Spill
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; CHECK-NEXT: mvc 168(8,%r15), 144(%r2) # 8-byte Folded Spill
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; CHECK-NEXT: brasl %r14, foo@PLT
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; CHECK-NEXT: algr %r2, %r7
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
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; CHECK-NEXT: algr %r2, %r6
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: algr %r2, %r13
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: algr %r2, %r12
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: algr %r2, %r8
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: algr %r2, %r9
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: algr %r2, %r10
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: algr %r2, %r11
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alg %r2, 160(%r15) # 8-byte Folded Reload
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: alg %r2, 168(%r15) # 8-byte Folded Reload
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
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; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
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; CHECK-NEXT: lmg %r6, %r15, 224(%r15)
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; CHECK-NEXT: br %r14
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%ptr1 = getelementptr i64, ptr %ptr0, i64 2
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%ptr2 = getelementptr i64, ptr %ptr0, i64 4
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%ptr3 = getelementptr i64, ptr %ptr0, i64 6
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%ptr4 = getelementptr i64, ptr %ptr0, i64 8
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%ptr5 = getelementptr i64, ptr %ptr0, i64 10
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%ptr6 = getelementptr i64, ptr %ptr0, i64 12
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%ptr7 = getelementptr i64, ptr %ptr0, i64 14
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%ptr8 = getelementptr i64, ptr %ptr0, i64 16
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%ptr9 = getelementptr i64, ptr %ptr0, i64 18
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%val0 = load i64, ptr %ptr0
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%val1 = load i64, ptr %ptr1
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%val2 = load i64, ptr %ptr2
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%val3 = load i64, ptr %ptr3
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%val4 = load i64, ptr %ptr4
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%val5 = load i64, ptr %ptr5
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%val6 = load i64, ptr %ptr6
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%val7 = load i64, ptr %ptr7
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%val8 = load i64, ptr %ptr8
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%val9 = load i64, ptr %ptr9
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%ret = call i64 @foo()
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%t0 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %ret, i64 %val0)
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%add0 = extractvalue {i64, i1} %t0, 0
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%obit0 = extractvalue {i64, i1} %t0, 1
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%t1 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add0, i64 %val1)
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%add1 = extractvalue {i64, i1} %t1, 0
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%obit1 = extractvalue {i64, i1} %t1, 1
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%res1 = or i1 %obit0, %obit1
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%t2 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add1, i64 %val2)
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%add2 = extractvalue {i64, i1} %t2, 0
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%obit2 = extractvalue {i64, i1} %t2, 1
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%res2 = or i1 %res1, %obit2
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%t3 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add2, i64 %val3)
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%add3 = extractvalue {i64, i1} %t3, 0
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%obit3 = extractvalue {i64, i1} %t3, 1
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%res3 = or i1 %res2, %obit3
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%t4 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add3, i64 %val4)
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%add4 = extractvalue {i64, i1} %t4, 0
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%obit4 = extractvalue {i64, i1} %t4, 1
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%res4 = or i1 %res3, %obit4
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%t5 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add4, i64 %val5)
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%add5 = extractvalue {i64, i1} %t5, 0
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%obit5 = extractvalue {i64, i1} %t5, 1
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%res5 = or i1 %res4, %obit5
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%t6 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add5, i64 %val6)
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%add6 = extractvalue {i64, i1} %t6, 0
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%obit6 = extractvalue {i64, i1} %t6, 1
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%res6 = or i1 %res5, %obit6
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%t7 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add6, i64 %val7)
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%add7 = extractvalue {i64, i1} %t7, 0
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%obit7 = extractvalue {i64, i1} %t7, 1
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%res7 = or i1 %res6, %obit7
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%t8 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add7, i64 %val8)
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%add8 = extractvalue {i64, i1} %t8, 0
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%obit8 = extractvalue {i64, i1} %t8, 1
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%res8 = or i1 %res7, %obit8
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%t9 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add8, i64 %val9)
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%add9 = extractvalue {i64, i1} %t9, 0
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%obit9 = extractvalue {i64, i1} %t9, 1
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%res9 = or i1 %res8, %obit9
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ret i1 %res9
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}
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declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
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