a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
64 lines
2.0 KiB
LLVM
64 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; Test 256-bit addition on z13 and higher
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v2, 16(%r3), 3
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; CHECK-NEXT: vl %v3, 16(%r2), 3
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vaccq %v4, %v3, %v2
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; CHECK-NEXT: vacccq %v5, %v1, %v0, %v4
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; CHECK-NEXT: vlgvg %r2, %v5, 1
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; CHECK-NEXT: vacq %v0, %v1, %v0, %v4
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; CHECK-NEXT: vaq %v1, %v3, %v2
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; CHECK-NEXT: vst %v1, 16(%r4), 3
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; CHECK-NEXT: vst %v0, 0(%r4), 3
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; CHECK-NEXT: br %r14
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%t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)
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%val = extractvalue {i256, i1} %t, 0
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%obit = extractvalue {i256, i1} %t, 1
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store i256 %val, ptr %res
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ret i1 %obit
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}
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define zeroext i1 @f2(i256 %a, i256 %b) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v2, 16(%r3), 3
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; CHECK-NEXT: vl %v3, 16(%r2), 3
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vaccq %v2, %v3, %v2
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; CHECK-NEXT: vacccq %v0, %v1, %v0, %v2
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; CHECK-NEXT: vlgvg %r2, %v0, 1
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; CHECK-NEXT: br %r14
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%t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)
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%obit = extractvalue {i256, i1} %t, 1
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ret i1 %obit
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}
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define i256 @f3(i256 %a, i256 %b) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v2, 16(%r4), 3
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; CHECK-NEXT: vl %v3, 16(%r3), 3
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vaccq %v4, %v3, %v2
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; CHECK-NEXT: vacq %v0, %v1, %v0, %v4
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; CHECK-NEXT: vaq %v1, %v3, %v2
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; CHECK-NEXT: vst %v1, 16(%r2), 3
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)
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%val = extractvalue {i256, i1} %t, 0
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ret i256 %val
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}
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declare {i256, i1} @llvm.uadd.with.overflow.i256(i256, i256) nounwind readnone
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