a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
75 lines
2.4 KiB
LLVM
75 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
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; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode().
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; SystemZISD::REPLICATE
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define i32 @f0(ptr %p0) {
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; CHECK-LABEL: f0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r2), 3
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; CHECK-NEXT: vgbm %v1, 0
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; CHECK-NEXT: vceqf %v0, %v0, %v1
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; CHECK-NEXT: vrepif %v1, 1
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; CHECK-NEXT: vnc %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: vlgvf %r2, %v0, 3
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; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; CHECK-NEXT: br %r14
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%a0 = load <4 x i32>, ptr %p0, align 8
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%cmp0 = icmp ne <4 x i32> %a0, zeroinitializer
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%zxt0 = zext <4 x i1> %cmp0 to <4 x i32>
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store <4 x i32> %zxt0, ptr %p0, align 8
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%ext0 = extractelement <4 x i32> %zxt0, i32 3
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br label %exit
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exit:
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; The vector icmp+zext involves a REPLICATE of 1's. If KnownBits reflects
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; this, DAGCombiner can see that the i32 icmp and zext here are not needed.
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%cmp1 = icmp ne i32 %ext0, 0
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%zxt1 = zext i1 %cmp1 to i32
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ret i32 %zxt1
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}
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; SystemZISD::JOIN_DWORDS (and REPLICATE)
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; The DAG XOR has JOIN_DWORDS and REPLICATE operands. With KnownBits properly set
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; for both these nodes, ICMP is used instead of TM during lowering because
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; adjustForRedundantAnd() succeeds.
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define void @f1(i64 %a0, i64 %a1) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: risbgn %r0, %r2, 63, 191, 0
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; CHECK-NEXT: risbgn %r1, %r3, 63, 191, 0
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; CHECK-NEXT: vlvgp %v0, %r0, %r1
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; CHECK-NEXT: vrepig %v1, 1
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; CHECK-NEXT: vx %v0, %v0, %v1
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; CHECK-NEXT: vlgvg %r0, %v0, 0
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; CHECK-NEXT: cgijlh %r0, 0, .LBB1_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: vlgvg %r0, %v0, 1
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; CHECK-NEXT: cgijlh %r0, 0, .LBB1_3
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: .LBB1_3:
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%1 = and i64 %a0, 1
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%2 = and i64 %a1, 1
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%3 = insertelement <2 x i64> undef, i64 %1, i32 0
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%4 = insertelement <2 x i64> %3, i64 %2, i32 1
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%5 = xor <2 x i64> %4, <i64 1, i64 1>
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%6 = extractelement <2 x i64> %5, i32 0
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%7 = and i64 %6, 1
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%8 = icmp eq i64 %7, 0
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br i1 %8, label %9, label %14
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; <label>:9: ; preds = %0
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%10 = extractelement <2 x i64> %5, i32 1
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%11 = and i64 %10, 1
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%12 = icmp eq i64 %11, 0
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br i1 %12, label %13, label %14
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; <label>:13: ; preds = %0
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unreachable
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; <label>:14: ; preds = %0
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unreachable
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}
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