59f7f35a90
Support passing and returning values of single-element vector types (i.e. <1 x i128> and <1 x fp128>). Now that i128 is a legal type, supporting these types can be done simply by providing a getRegisterTypeForCallingConv implementation that handles them. Fixes https://github.com/llvm/llvm-project/issues/61291
35 lines
968 B
LLVM
35 lines
968 B
LLVM
; Test vector addition on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test a v4f32 addition.
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define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vfasb %v24, %v26, %v28
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; CHECK: br %r14
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%ret = fadd <4 x float> %val1, %val2
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ret <4 x float> %ret
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}
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; Test an f32 addition that uses vector registers.
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define float @f2(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: wfasb %f0, %v24, %v26
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; CHECK: br %r14
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%scalar1 = extractelement <4 x float> %val1, i32 0
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%scalar2 = extractelement <4 x float> %val2, i32 0
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%ret = fadd float %scalar1, %scalar2
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ret float %ret
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}
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; Test a v1f128 addition.
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define <1 x fp128> @f3(<1 x fp128> %dummy, <1 x fp128> %val1,
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<1 x fp128> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: wfaxb %v24, %v26, %v28
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; CHECK: br %r14
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%ret = fadd <1 x fp128> %val1, %val2
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ret <1 x fp128> %ret
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}
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