bbcebec3af
This PR resolves https://github.com/llvm/llvm-project/issues/144513 The modification include five pattern : 1.vselect Cond, 0, 0 → 0 2.vselect Cond, -1, 0 → bitcast Cond 3.vselect Cond, -1, x → or Cond, x 4.vselect Cond, x, 0 → and Cond, x 5.vselect Cond, 000..., X -> andn Cond, X 1-4 have been migrated to DAGCombine. 5 still in x86 code. The reason is that you cannot use the andn instruction directly in DAGCombine, you can only use and+xor, which will introduce optimization order issues. For example, in the x86 backend, select Cond, 0, x → (~Cond) & x, the backend will first check whether the cond node of (~Cond) is a setcc node. If so, it will modify the comparison operator of the condition.So the x86 backend cannot complete the optimization of andn.In short, I think it is a better choice to keep the pattern of vselect Cond, 000..., X instead of and+xor in combineDAG. For commit, the first is code changes and x86 test(note 1), the second is tests in other backend(node 2). --------- Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
98 lines
3.0 KiB
LLVM
98 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test vector maximum/minimum with a zero splat on z14.
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define <2 x double> @f1(<2 x double> %val) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfmaxdb %v24, %v24, %v0, 4
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; CHECK-NEXT: br %r14
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%cmp = fcmp ogt <2 x double> %val, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val, <2 x double> zeroinitializer
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ret <2 x double> %ret
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}
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define <2 x double> @f2(<2 x double> %val) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfmindb %v24, %v24, %v0, 4
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; CHECK-NEXT: br %r14
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%cmp = fcmp olt <2 x double> %val, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val, <2 x double> zeroinitializer
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ret <2 x double> %ret
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}
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define <4 x float> @f3(<4 x float> %val) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfmaxsb %v24, %v24, %v0, 4
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; CHECK-NEXT: br %r14
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%cmp = fcmp ogt <4 x float> %val, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
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ret <4 x float> %ret
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}
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define <4 x float> @f4(<4 x float> %val) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfminsb %v24, %v24, %v0, 4
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; CHECK-NEXT: br %r14
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%cmp = fcmp olt <4 x float> %val, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
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ret <4 x float> %ret
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}
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define <2 x double> @f5(<2 x double> %val) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfchedb %v0, %v0, %v24
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; CHECK-NEXT: vnc %v24, %v24, %v0
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; CHECK-NEXT: br %r14
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%cmp = fcmp ugt <2 x double> %val, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val, <2 x double> zeroinitializer
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ret <2 x double> %ret
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}
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define <2 x double> @f6(<2 x double> %val) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfchedb %v0, %v24, %v0
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; CHECK-NEXT: vnc %v24, %v24, %v0
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; CHECK-NEXT: br %r14
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%cmp = fcmp ult <2 x double> %val, zeroinitializer
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%ret = select <2 x i1> %cmp, <2 x double> %val, <2 x double> zeroinitializer
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ret <2 x double> %ret
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}
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define <4 x float> @f7(<4 x float> %val) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfchesb %v0, %v0, %v24
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; CHECK-NEXT: vnc %v24, %v24, %v0
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; CHECK-NEXT: br %r14
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%cmp = fcmp ugt <4 x float> %val, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
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ret <4 x float> %ret
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}
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define <4 x float> @f8(<4 x float> %val) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: vfchesb %v0, %v24, %v0
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; CHECK-NEXT: vnc %v24, %v24, %v0
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; CHECK-NEXT: br %r14
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%cmp = fcmp ult <4 x float> %val, zeroinitializer
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%ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
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ret <4 x float> %ret
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}
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