a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
183 lines
3.9 KiB
LLVM
183 lines
3.9 KiB
LLVM
; Test vector loads.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8 loads.
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define <16 x i8> @f1(ptr %ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <16 x i8>, ptr %ptr
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ret <16 x i8> %ret
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}
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; Test v8i16 loads.
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define <8 x i16> @f2(ptr %ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <8 x i16>, ptr %ptr
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ret <8 x i16> %ret
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}
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; Test v4i32 loads.
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define <4 x i32> @f3(ptr %ptr) {
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; CHECK-LABEL: f3:
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <4 x i32>, ptr %ptr
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ret <4 x i32> %ret
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}
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; Test v2i64 loads.
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define <2 x i64> @f4(ptr %ptr) {
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; CHECK-LABEL: f4:
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <2 x i64>, ptr %ptr
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ret <2 x i64> %ret
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}
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; Test v4f32 loads.
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define <4 x float> @f5(ptr %ptr) {
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; CHECK-LABEL: f5:
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <4 x float>, ptr %ptr
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ret <4 x float> %ret
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}
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; Test v2f64 loads.
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define <2 x double> @f6(ptr %ptr) {
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; CHECK-LABEL: f6:
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <2 x double>, ptr %ptr
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ret <2 x double> %ret
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}
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; Test the highest aligned in-range offset.
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define <16 x i8> @f7(ptr %base) {
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; CHECK-LABEL: f7:
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; CHECK: vl %v24, 4080(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, ptr %base, i64 255
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%ret = load <16 x i8>, ptr %ptr
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ret <16 x i8> %ret
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}
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; Test the highest unaligned in-range offset.
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define <16 x i8> @f8(ptr %base) {
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; CHECK-LABEL: f8:
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; CHECK: vl %v24, 4095(%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, ptr %base, i64 4095
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%ret = load <16 x i8>, ptr %addr, align 1
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ret <16 x i8> %ret
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}
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; Test the next offset up, which requires separate address logic,
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define <16 x i8> @f9(ptr %base) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, 4096
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, ptr %base, i64 256
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%ret = load <16 x i8>, ptr %ptr
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ret <16 x i8> %ret
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}
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; Test negative offsets, which also require separate address logic,
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define <16 x i8> @f10(ptr %base) {
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; CHECK-LABEL: f10:
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; CHECK: aghi %r2, -16
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, ptr %base, i64 -1
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%ret = load <16 x i8>, ptr %ptr
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ret <16 x i8> %ret
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}
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; Check that indexes are allowed.
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define <16 x i8> @f11(ptr %base, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: vl %v24, 0(%r3,%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, ptr %base, i64 %index
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%ret = load <16 x i8>, ptr %addr, align 1
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ret <16 x i8> %ret
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}
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; Test v2i8 loads.
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define <2 x i8> @f12(ptr %ptr) {
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; CHECK-LABEL: f12:
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; CHECK: vlreph %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <2 x i8>, ptr %ptr
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ret <2 x i8> %ret
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}
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; Test v4i8 loads.
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define <4 x i8> @f13(ptr %ptr) {
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; CHECK-LABEL: f13:
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; CHECK: vlrepf %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <4 x i8>, ptr %ptr
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ret <4 x i8> %ret
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}
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; Test v8i8 loads.
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define <8 x i8> @f14(ptr %ptr) {
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; CHECK-LABEL: f14:
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; CHECK: vlrepg %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <8 x i8>, ptr %ptr
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ret <8 x i8> %ret
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}
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; Test v2i16 loads.
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define <2 x i16> @f15(ptr %ptr) {
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; CHECK-LABEL: f15:
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; CHECK: vlrepf %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <2 x i16>, ptr %ptr
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ret <2 x i16> %ret
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}
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; Test v4i16 loads.
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define <4 x i16> @f16(ptr %ptr) {
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; CHECK-LABEL: f16:
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; CHECK: vlrepg %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <4 x i16>, ptr %ptr
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ret <4 x i16> %ret
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}
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; Test v2i32 loads.
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define <2 x i32> @f17(ptr %ptr) {
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; CHECK-LABEL: f17:
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; CHECK: vlrepg %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <2 x i32>, ptr %ptr
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ret <2 x i32> %ret
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}
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; Test v2f32 loads.
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define <2 x float> @f18(ptr %ptr) {
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; CHECK-LABEL: f18:
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; CHECK: vlrepg %v24, 0(%r2)
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; CHECK: br %r14
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%ret = load <2 x float>, ptr %ptr
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ret <2 x float> %ret
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}
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; Test quadword-aligned loads.
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define <16 x i8> @f19(ptr %ptr) {
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; CHECK-LABEL: f19:
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; CHECK: vl %v24, 0(%r2), 4
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; CHECK: br %r14
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%ret = load <16 x i8>, ptr %ptr, align 16
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ret <16 x i8> %ret
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}
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