8998ff53c9
This reverts commit 0a762ec1b09d96734a3462f8792a5574d089b24d. Some CPUs enable fp64 by default (such as cortex-m7). When specifying a single-precision fpu with them like -mfpu=fpv5-sp-d16, the fp64 feature will be disabled, but fpreg64 will not. We need to disable them both correctly under clang in order for the backend to be able to use the reliably. In the meantime this reverts 0a762ec1b09d96734 until that issue is fixed.
49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m4 -mattr=-vfp2 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 -mattr=+vfp4,-fp64 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 -mattr=+vfp3 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
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define float @float_in_reg(float %a, float %b) {
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entry:
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; CHECK-LABEL: float_in_reg:
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; SOFT: mov r0, r1
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; HARD: vmov.f32 s0, s1
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; CHECK-NEXT: bx lr
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ret float %b
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}
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define double @double_in_reg(double %a, double %b) {
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entry:
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; CHECK-LABEL: double_in_reg:
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; SOFT: mov r1, r3
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; SOFT: mov r0, r2
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; SP: vmov.f32 s0, s2
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; SP: vmov.f32 s1, s3
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; DP: vmov.f64 d0, d1
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; CHECK-NEXT: bx lr
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ret double %b
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}
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define float @float_on_stack(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, float %i) {
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; CHECK-LABEL: float_on_stack:
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; SOFT: ldr r0, [sp, #48]
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; HARD: vldr s0, [sp]
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; CHECK-NEXT: bx lr
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ret float %i
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}
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define double @double_on_stack(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) {
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; CHECK-LABEL: double_on_stack:
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; SOFT: ldrd r0, r1, [sp, #48]
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; HARD: vldr d0, [sp]
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; CHECK-NEXT: bx lr
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ret double %i
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}
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define double @double_not_split(double %a, double %b, double %c, double %d, double %e, double %f, double %g, float %h, double %i) {
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; CHECK-LABEL: double_not_split:
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; SOFT: ldrd r0, r1, [sp, #48]
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; HARD: vldr d0, [sp]
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; CHECK-NEXT: bx lr
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ret double %i
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}
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