c65b4d64d4
Alignment of an alloca in IR can be lower than the preferred alignment on purpose, but this override essentially treats the preferred alignment as the minimum alignment. The patch changes this behavior to always use the specified alignment. If alignment is not set explicitly in LLVM IR, it is set to DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign. Tests are changed as well: explicit alignment is increased to match the preferred alignment if it changes output, or omitted when it is hard to determine the right value (e.g. for pointers, some structs, or weird types). Differential Revision: https://reviews.llvm.org/D135462
255 lines
7.3 KiB
LLVM
255 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc void @vstrw32() {
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; CHECK-LABEL: vstrw32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vstrw.32 q0, [sp, #8]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [4 x i32], align 4
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%g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2
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store <4 x i32> zeroinitializer, ptr %g, align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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ret void
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}
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define arm_aapcs_vfpcc void @vstrh16() {
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; CHECK-LABEL: vstrh16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vstrh.16 q0, [sp, #4]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [8 x i16], align 2
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%g = getelementptr inbounds [8 x i16], ptr %d, i32 0, i32 2
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store <8 x i16> zeroinitializer, ptr %g, align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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ret void
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}
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define arm_aapcs_vfpcc void @vstrb8() {
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; CHECK-LABEL: vstrb8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vstrh.16 q0, [sp, #2]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [16 x i8], align 4
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%g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2
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store <16 x i8> zeroinitializer, ptr %g, align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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ret void
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}
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define arm_aapcs_vfpcc void @vstrh32() {
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; CHECK-LABEL: vstrh32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vmov.i32 q0, #0x6
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; CHECK-NEXT: vstrh.32 q0, [r0, #4]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [4 x i16], align 4
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%g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2
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store <4 x i16> <i16 6, i16 6, i16 6, i16 6>, ptr %g, align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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ret void
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}
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define arm_aapcs_vfpcc void @vstrb32() {
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; CHECK-LABEL: vstrb32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: vmov.i32 q0, #0x6
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; CHECK-NEXT: vstrb.32 q0, [r0, #2]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [4 x i8], align 4
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%g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2
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store <4 x i8> <i8 6, i8 6, i8 6, i8 6>, ptr %g, align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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ret void
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}
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define arm_aapcs_vfpcc void @vstrb16() {
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; CHECK-LABEL: vstrb16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: vstrb.16 q0, [r0, #2]
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; CHECK-NEXT: bl func
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [8 x i8], align 4
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%g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2
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store <8 x i8> zeroinitializer, ptr %g, align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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ret void
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}
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define arm_aapcs_vfpcc <4 x i32> @vldrw32() {
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; CHECK-LABEL: vldrw32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: bl func
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; CHECK-NEXT: vldrw.u32 q0, [sp, #8]
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [4 x i32], align 4
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call arm_aapcs_vfpcc void @func(ptr %d)
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%g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2
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%l = load <4 x i32>, ptr %g, align 2
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ret <4 x i32> %l
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}
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define arm_aapcs_vfpcc <8 x i16> @vldrh16() {
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; CHECK-LABEL: vldrh16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: bl func
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; CHECK-NEXT: vldrh.u16 q0, [sp, #4]
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [8 x i16], align 2
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call arm_aapcs_vfpcc void @func(ptr %d)
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%g = getelementptr inbounds [8 x i16], ptr %d, i32 0, i32 2
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%l = load <8 x i16>, ptr %g, align 2
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ret <8 x i16> %l
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}
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define arm_aapcs_vfpcc <16 x i8> @vldrb8() {
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; CHECK-LABEL: vldrb8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: bl func
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; CHECK-NEXT: vldrh.u16 q0, [sp, #2]
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%d = alloca [16 x i8], align 4
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call arm_aapcs_vfpcc void @func(ptr %d)
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%g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2
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%l = load <16 x i8>, ptr %g, align 2
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ret <16 x i8> %l
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}
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define arm_aapcs_vfpcc <4 x i16> @vldrh32() {
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; CHECK-LABEL: vldrh32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r4, sp
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl func
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; CHECK-NEXT: vldrh.u32 q0, [r4, #4]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%d = alloca [4 x i16], align 4
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call arm_aapcs_vfpcc void @func(ptr %d)
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%g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2
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%l = load <4 x i16>, ptr %g, align 2
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ret <4 x i16> %l
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}
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define arm_aapcs_vfpcc <4 x i8> @vldrb32() {
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; CHECK-LABEL: vldrb32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: add r4, sp, #4
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl func
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; CHECK-NEXT: vldrb.u32 q0, [r4, #2]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%d = alloca [4 x i8], align 4
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call arm_aapcs_vfpcc void @func(ptr %d)
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%g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2
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%l = load <4 x i8>, ptr %g, align 2
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ret <4 x i8> %l
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}
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define arm_aapcs_vfpcc <8 x i8> @vldrb16() {
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; CHECK-LABEL: vldrb16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: mov r4, sp
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: bl func
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; CHECK-NEXT: vldrb.u16 q0, [r4, #2]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%d = alloca [8 x i8], align 4
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call arm_aapcs_vfpcc void @func(ptr %d)
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%g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2
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%l = load <8 x i8>, ptr %g, align 2
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ret <8 x i8> %l
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}
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declare dso_local arm_aapcs_vfpcc void @func(...)
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