1b12b1a335
The expansion of the various MOVi32imm pseudo-instructions works by splitting the operand into components (either halfwords or bytes) and emitting instructions to combine those components into the final result. When the operand is an immediate with some components being zero this can result in pointless instructions that just add zero. Avoid this by restructuring things so that a separate function handles splitting the operand into components, then don't emit the component if it is a zero immediate. This is straightforward for movw/movt, where we just don't emit the movt if it's zero, but the thumb1 expansion using mov/add/lsl is more complex, as even when we don't emit a given byte we still need to get the shift correct. Differential Revision: https://reviews.llvm.org/D154943
191 lines
5.1 KiB
LLVM
191 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumb-linux-androideabi -mcpu=arm1156t2-s -mattr=+thumb2 -verify-machineinstrs | FileCheck %s -check-prefix=THUMB
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; RUN: llc < %s -mtriple=arm-linux-androideabi -mcpu=arm1156t2-s -verify-machineinstrs | FileCheck %s -check-prefix=ARM
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; Just to prevent the alloca from being optimized away
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declare void @dummy_use(ptr, i32)
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define void @test_basic() #0 {
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; THUMB-LABEL: test_basic:
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; THUMB: @ %bb.0:
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; THUMB-NEXT: push {r4, r5}
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; THUMB-NEXT: mrc p15, #0, r4, c13, c0, #3
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; THUMB-NEXT: mov r5, sp
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; THUMB-NEXT: ldr.w r4, [r4, #252]
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; THUMB-NEXT: cmp r4, r5
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; THUMB-NEXT: bls .LBB0_2
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; THUMB-NEXT: @ %bb.1:
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; THUMB-NEXT: mov r4, #48
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; THUMB-NEXT: mov r5, #0
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; THUMB-NEXT: push {lr}
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; THUMB-NEXT: bl __morestack
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; THUMB-NEXT: ldr lr, [sp], #4
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; THUMB-NEXT: pop {r4, r5}
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; THUMB-NEXT: bx lr
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; THUMB-NEXT: .LBB0_2:
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; THUMB-NEXT: pop {r4, r5}
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; THUMB-NEXT: .save {r7, lr}
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; THUMB-NEXT: push {r7, lr}
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; THUMB-NEXT: .pad #40
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; THUMB-NEXT: sub sp, #40
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; THUMB-NEXT: mov r0, sp
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; THUMB-NEXT: movs r1, #10
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; THUMB-NEXT: bl dummy_use
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; THUMB-NEXT: add sp, #40
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; THUMB-NEXT: pop {r7, pc}
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;
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; ARM-LABEL: test_basic:
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; ARM: @ %bb.0:
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; ARM-NEXT: push {r4, r5}
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; ARM-NEXT: mrc p15, #0, r4, c13, c0, #3
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; ARM-NEXT: mov r5, sp
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; ARM-NEXT: ldr r4, [r4, #252]
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; ARM-NEXT: cmp r4, r5
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; ARM-NEXT: bls .LBB0_2
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; ARM-NEXT: @ %bb.1:
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; ARM-NEXT: mov r4, #48
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; ARM-NEXT: mov r5, #0
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; ARM-NEXT: stmdb sp!, {lr}
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; ARM-NEXT: bl __morestack
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; ARM-NEXT: ldm sp!, {lr}
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; ARM-NEXT: pop {r4, r5}
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; ARM-NEXT: bx lr
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; ARM-NEXT: .LBB0_2:
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; ARM-NEXT: pop {r4, r5}
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; ARM-NEXT: .save {r11, lr}
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; ARM-NEXT: push {r11, lr}
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; ARM-NEXT: .pad #40
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; ARM-NEXT: sub sp, sp, #40
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; ARM-NEXT: mov r0, sp
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; ARM-NEXT: mov r1, #10
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; ARM-NEXT: bl dummy_use
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; ARM-NEXT: add sp, sp, #40
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; ARM-NEXT: pop {r11, pc}
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%mem = alloca i32, i32 10
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call void @dummy_use (ptr %mem, i32 10)
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ret void
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}
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define void @test_large() #0 {
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%mem = alloca i32, i32 10000
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call void @dummy_use (ptr %mem, i32 0)
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ret void
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; THUMB-LABEL: test_large:
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; THUMB: push {r4, r5}
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; THUMB-NEXT: mov r5, sp
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; THUMB-NEXT: movw r4, #40192
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; THUMB-NEXT: sub r5, r5, r4
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; THUMB-NEXT: mrc p15, #0, r4, c13, c0, #3
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; THUMB-NEXT: ldr.w r4, [r4, #252]
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; THUMB-NEXT: cmp r4, r5
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; THUMB-NEXT: bls .LBB1_2
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; THUMB: movw r4, #40192
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; THUMB-NEXT: mov r5, #0
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; THUMB-NEXT: push {lr}
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; THUMB-NEXT: bl __morestack
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; THUMB-NEXT: ldr lr, [sp], #4
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; THUMB-NEXT: pop {r4, r5}
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; THUMB-NEXT: bx lr
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; THUMB: pop {r4, r5}
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; ARM-LABEL: test_large:
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; ARM: push {r4, r5}
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; ARM-NEXT: ldr r4, .LCPI1_0
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; ARM-NEXT: sub r5, sp, r4
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; ARM-NEXT: mrc p15, #0, r4, c13, c0, #3
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; ARM-NEXT: ldr r4, [r4, #252]
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; ARM-NEXT: cmp r4, r5
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; ARM-NEXT: bls .LBB1_2
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; ARM: ldr r4, .LCPI1_0
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; ARM-NEXT: mov r5, #0
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; ARM-NEXT: stmdb sp!, {lr}
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; ARM-NEXT: bl __morestack
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; ARM-NEXT: ldm sp!, {lr}
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; ARM-NEXT: pop {r4, r5}
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; ARM-NEXT: bx lr
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; ARM: pop {r4, r5}
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; ARM: .LCPI1_0:
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; ARM-NEXT: .long 40192
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}
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define fastcc void @test_fastcc_large() #0 {
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%mem = alloca i32, i32 10000
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call void @dummy_use (ptr %mem, i32 0)
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ret void
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; THUMB-LABEL: test_fastcc_large:
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; THUMB: push {r4, r5}
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; THUMB-NEXT: mov r5, sp
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; THUMB-NEXT: movw r4, #40192
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; THUMB-NEXT: sub r5, r5, r4
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; THUMB-NEXT: mrc p15, #0, r4, c13, c0, #3
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; THUMB-NEXT: ldr.w r4, [r4, #252]
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; THUMB-NEXT: cmp r4, r5
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; THUMB-NEXT: bls .LBB2_2
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; THUMB: movw r4, #40192
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; THUMB-NEXT: mov r5, #0
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; THUMB-NEXT: push {lr}
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; THUMB-NEXT: bl __morestack
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; THUMB-NEXT: ldr lr, [sp], #4
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; THUMB-NEXT: pop {r4, r5}
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; THUMB-NEXT: bx lr
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; THUMB: pop {r4, r5}
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; ARM-LABEL: test_fastcc_large:
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; ARM: push {r4, r5}
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; ARM-NEXT: ldr r4, .LCPI2_0
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; ARM-NEXT: sub r5, sp, r4
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; ARM-NEXT: mrc p15, #0, r4, c13, c0, #3
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; ARM-NEXT: ldr r4, [r4, #252]
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; ARM-NEXT: cmp r4, r5
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; ARM-NEXT: bls .LBB2_2
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; ARM: ldr r4, .LCPI2_0
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; ARM-NEXT: mov r5, #0
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; ARM-NEXT: stmdb sp!, {lr}
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; ARM-NEXT: bl __morestack
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; ARM-NEXT: ldm sp!, {lr}
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; ARM-NEXT: pop {r4, r5}
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; ARM-NEXT: bx lr
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; ARM: .LCPI2_0:
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; ARM-NEXT: .long 40192
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}
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declare void @panic() unnamed_addr
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; We used to crash while compiling the following function.
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; THUMB-LABEL: build_should_not_segfault:
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; ARM-LABEL: build_should_not_segfault:
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define void @build_should_not_segfault(i8 %x) unnamed_addr #0 {
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start:
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%_0 = icmp ult i8 %x, 16
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%or.cond = select i1 undef, i1 true, i1 %_0
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br i1 %or.cond, label %bb1, label %bb2
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bb1:
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ret void
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bb2:
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call void @panic()
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unreachable
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}
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attributes #0 = { "split-stack" }
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