d6f9278ae9
In late 2021, both Intel and AMD finally documented that every AVX-capable CPU has always been guaranteed to execute aligned 16-byte loads/stores atomically, and further, guaranteed that all future CPUs with AVX will do so as well. Therefore, we may use normal SSE 128-bit load/store instructions to implement atomics, if AVX is enabled. Per AMD64 Architecture Programmer's manual, 7.3.2 Access Atomicity: > Processors that report [AVX] extend the atomicity for cacheable, > naturally-aligned single loads or stores from a quadword to a double > quadword. Per Intel's SDM: > Processors that enumerate support for Intel(R) AVX guarantee that the > 16-byte memory operations performed by the following instructions will > always be carried out atomically: > - MOVAPD, MOVAPS, and MOVDQA. > - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. > - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded with > EVEX.128 and k0 (masking disabled). This was also confirmed to be true for Zhaoxin CPUs with AVX, in https://gcc.gnu.org/PR104688
34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
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; Quick test to ensure that atomics which are not naturally-aligned
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; emit unsized libcalls, and aren't emitted as native instructions or
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; sized libcalls.
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define void @test_i32(ptr %a) nounwind {
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; CHECK-LABEL: test_i32:
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; CHECK: callq __atomic_load
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; CHECK: callq __atomic_store
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; CHECK: callq __atomic_exchange
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; CHECK: callq __atomic_compare_exchange
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; CHECK: callq __atomic_compare_exchange
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%t0 = load atomic i32, ptr %a seq_cst, align 2
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store atomic i32 1, ptr %a seq_cst, align 2
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%t1 = atomicrmw xchg ptr %a, i32 1 seq_cst, align 2
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%t3 = atomicrmw add ptr %a, i32 2 seq_cst, align 2
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%t2 = cmpxchg ptr %a, i32 0, i32 1 seq_cst seq_cst, align 2
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ret void
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}
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define void @test_i128(ptr %a) nounwind {
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; CHECK-LABEL: test_i128:
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; CHECK: callq __atomic_load
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; CHECK: callq __atomic_store
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; CHECK: callq __atomic_exchange
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; CHECK: callq __atomic_compare_exchange
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%t0 = load atomic i128, ptr %a seq_cst, align 8
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store atomic i128 1, ptr %a seq_cst, align 8
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%t1 = atomicrmw xchg ptr %a, i128 1 seq_cst, align 8
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%t2 = atomicrmw add ptr %a, i128 2 seq_cst, align 8
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%t3 = cmpxchg ptr %a, i128 0, i128 1 seq_cst seq_cst, align 8
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ret void
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}
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