4d629f9744
In review of bbde6b, I had originally proposed that we support the legacy text format. As review evolved, it bacame clear this had been a bad idea (too much complexity), but in order to let that patch finally move forward, I approved the change with the variant. This change undoes the variant, and updates all the tests to just use the array form.
108 lines
5.2 KiB
YAML
108 lines
5.2 KiB
YAML
# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=x86-avoid-SFB | FileCheck %s
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--- |
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; ModuleID = '../test50419-2.ll'
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source_filename = "nice.c"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@.str = private unnamed_addr constant [3 x i8] c"%u\00", align 1
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define i32 @test_offset() #0 {
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entry:
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%a = alloca [36 x i32], align 16
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%z = alloca [36 x i32], align 16
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%0 = bitcast ptr %z to ptr
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%scevgep = getelementptr inbounds [36 x i32], ptr %a, i64 0, i64 1
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%scevgep40 = bitcast ptr %scevgep to ptr
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%arrayidx.9 = getelementptr inbounds [36 x i32], ptr %a, i64 0, i64 9
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%1 = load i32, ptr %arrayidx.9, align 4
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%add.9 = add i32 %1, 9
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store i32 %add.9, ptr %arrayidx.9, align 4
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call void @llvm.memcpy.p0.p0.i64(ptr nonnull align 16 %0, ptr nonnull align 4 %scevgep40, i64 136, i1 false)
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ret i32 %1
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #1
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(ptr, ptr) #2
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attributes #0 = { "target-cpu"="core-avx2" }
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attributes #1 = { argmemonly nounwind "target-cpu"="core-avx2" }
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attributes #2 = { nounwind }
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...
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---
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name: test_offset
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32, preferred-register: '' }
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- { id: 1, class: gr32, preferred-register: '' }
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- { id: 2, class: vr256, preferred-register: '' }
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- { id: 3, class: vr256, preferred-register: '' }
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- { id: 4, class: vr256, preferred-register: '' }
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- { id: 5, class: gr64, preferred-register: '' }
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- { id: 6, class: vr256, preferred-register: '' }
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liveins:
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 16
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack:
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stack:
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- { id: 0, name: a, type: default, offset: 0, size: 144, alignment: 16,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: z, type: default, offset: 0, size: 144, alignment: 16,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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constants:
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body: |
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bb.0.entry:
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%0:gr32 = MOV32rm %stack.0.a, 1, $noreg, 36, $noreg :: (dereferenceable load (s32) from %ir.arrayidx.9)
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%1:gr32 = ADD32ri8 %0, 9, implicit-def dead $eflags
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MOV32mr %stack.0.a, 1, $noreg, 36, $noreg, killed %1 :: (store (s32) into %ir.arrayidx.9)
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%2:vr256 = VMOVUPSYrm %stack.0.a, 1, $noreg, 4, $noreg :: (dereferenceable load (s256) from %ir.scevgep40, align 4)
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VMOVUPSYmr %stack.1.z, 1, $noreg, 0, $noreg, killed %2 :: (store (s256) into %ir.0, align 16)
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%3:vr256 = VMOVUPSYrm %stack.0.a, 1, $noreg, 68, $noreg :: (dereferenceable load (s256) from %ir.scevgep40 + 64, align 4)
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VMOVUPSYmr %stack.1.z, 1, $noreg, 64, $noreg, killed %3 :: (store (s256) into %ir.0 + 64, align 16)
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%4:vr256 = VMOVUPSYrm %stack.0.a, 1, $noreg, 100, $noreg :: (dereferenceable load (s256) from %ir.scevgep40 + 96, align 4)
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VMOVUPSYmr %stack.1.z, 1, $noreg, 96, $noreg, killed %4 :: (store (s256) into %ir.0 + 96, align 16)
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%5:gr64 = MOV64rm %stack.0.a, 1, $noreg, 132, $noreg :: (dereferenceable load (s64) from %ir.scevgep40 + 128, align 4)
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MOV64mr %stack.1.z, 1, $noreg, 128, $noreg, killed %5 :: (store (s64) into %ir.0 + 128, align 16)
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; CHECK: gr32 = MOV32rm %stack.0.a, 1, $noreg, 36, $noreg :: (dereferenceable load (s32) from %ir.scevgep40 + 32)
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; CHECK-NEXT: MOV32mr %stack.1.z, 1, $noreg, 32, $noreg, killed %7 :: (store (s32) into %ir.0 + 32, align 16)
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; CHECK-NEXT: %8:vr128 = VMOVUPSrm %stack.0.a, 1, $noreg, 40, $noreg :: (dereferenceable load (s128) from %ir.scevgep40 + 36, align 4)
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; CHECK-NEXT: VMOVUPSmr %stack.1.z, 1, $noreg, 36, $noreg, killed %8 :: (store (s128) into %ir.0 + 36, align 4, basealign 16)
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; CHECK-NEXT: %9:gr64 = MOV64rm %stack.0.a, 1, $noreg, 56, $noreg :: (dereferenceable load (s64) from %ir.scevgep40 + 52, align 4)
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; CHECK-NEXT: MOV64mr %stack.1.z, 1, $noreg, 52, $noreg, killed %9 :: (store (s64) into %ir.0 + 52, align 4, basealign 16)
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; CHECK-NEXT: %10:gr32 = MOV32rm %stack.0.a, 1, $noreg, 64, $noreg :: (dereferenceable load (s32) from %ir.scevgep40 + 60)
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; CHECK-NEXT: MOV32mr %stack.1.z, 1, $noreg, 60, $noreg, killed %10 :: (store (s32) into %ir.0 + 60, basealign 16)
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%6:vr256 = VMOVUPSYrm %stack.0.a, 1, $noreg, 36, $noreg :: (dereferenceable load (s256) from %ir.scevgep40 + 32, align 4)
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VMOVUPSYmr %stack.1.z, 1, $noreg, 32, $noreg, killed %6 :: (store (s256) into %ir.0 + 32, align 16)
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$eax = COPY %0
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RET 0, $eax
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...
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