76e14deb4a
BreakFalseDeps picks the best register for undef operands if instructions have false dependency. The problem is if the instruction is close to the beginning of the function, ReachingDefAnalysis is over optimism to the unused registers, which results in collision with registers just defined in the caller. This patch changes the selection of undef register in an reverse order, which reduces the probability of register collisions between caller and callee. It brings improvement in some of our internal benchmarks with negligible effect on other benchmarks.
100 lines
2.7 KiB
LLVM
100 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx512f -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
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define double @long_to_double_rr(i64 %a) {
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; SSE2-LABEL: long_to_double_rr:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: cvtsi2sd %rdi, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_double_rr:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsi2sd %rdi, %xmm15, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sitofp i64 %a to double
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ret double %0
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}
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define double @long_to_double_rm(ptr %a) {
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; SSE2-LABEL: long_to_double_rm:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: cvtsi2sdq (%rdi), %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_double_rm:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsi2sdq (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = load i64, ptr %a
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define double @long_to_double_rm_optsize(ptr %a) optsize {
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; SSE2-LABEL: long_to_double_rm_optsize:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: cvtsi2sdq (%rdi), %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_double_rm_optsize:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsi2sdq (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = load i64, ptr %a
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define float @long_to_float_rr(i64 %a) {
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; SSE2-LABEL: long_to_float_rr:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: cvtsi2ss %rdi, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_float_rr:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsi2ss %rdi, %xmm15, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sitofp i64 %a to float
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ret float %0
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}
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define float @long_to_float_rm(ptr %a) {
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; SSE2-LABEL: long_to_float_rm:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: cvtsi2ssq (%rdi), %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_float_rm:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsi2ssq (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = load i64, ptr %a
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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define float @long_to_float_rm_optsize(ptr %a) optsize {
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; SSE2-LABEL: long_to_float_rm_optsize:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: cvtsi2ssq (%rdi), %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_float_rm_optsize:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsi2ssq (%rdi), %xmm15, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = load i64, ptr %a
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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