e59a619acf
The SelectionDAG asm-lowering code can already handle conversion of other vector types to MMX if needed.
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx | FileCheck %s
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;; Verify that the mmx 'y' constraint works with arbitrary IR types.
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define <2 x i32> @test_mmx_asm(<2 x i32> %a) nounwind {
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; CHECK-LABEL: test_mmx_asm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdq2q %xmm0, %mm0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # %mm0 = %mm0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # %mm0 = %mm0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq2dq %mm0, %xmm0
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "# $0 = $1", "=y,y"(<2 x i32> %a)
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%2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=y,y"(i64 %1)
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ret <2 x i32> %2
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}
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;; And same thing with the 'Ym' constraint.
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define <2 x i32> @test_mmx_asm_Ym(<2 x i32> %a) nounwind {
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; CHECK-LABEL: test_mmx_asm_Ym:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdq2q %xmm0, %mm0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # %mm0 = %mm0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # %mm0 = %mm0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq2dq %mm0, %xmm0
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "# $0 = $1", "=^Ym,^Ym"(<2 x i32> %a)
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%2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=^Ym,^Ym"(i64 %1)
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ret <2 x i32> %2
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}
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